The Platform Viability theme

These are the tasks of the viability theme, as set forth in the 2010 GSRC Proposal.

Task 5.4.1. -- Scalable and Low-Cost Post-Silicon Validation
PIs: Valeria Bertacco, Tim Cheng

Task 5.4.2. -- Hierarchical, Signature-Driven AMS/RF Test and Validation
PIs: Abhijit Chatterjee, Tim Cheng

Task 5.4.3. -- Low-Cost SoC On-chip Test and Diagnosis
PIs: Tim Cheng, Subhasish Mitra

Task 5.4.4. -- Uncore Functional, Performance, and Power Verification
PIs: Sharad Malik, Sanjit A. Seshia

Task 5.4.5. -- Design and Verification of Concurrency Abstractions
PIs: Rajeev Alur, Sharad Malik

Task 5.4.6. -- Analog Circuit Verification by Statistical Model Checking
PI: Edmund M. Clarke

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