Faculty Tasks Students Papers Demos Posters Talks
The Future of Data Centers - GSRC Workshop
E-Workshop on the Future of Data Centers - GSRC Overview
Rethinking server design for the ensemble - Server and rack efficiency
Thermal Issues for Future Data Centers - Challenges, Innovative Solutions
Heterogeneity and Scale -- Challenges for Resource Management
Storage Class Memory and the data center of the future
Networking and Consolidation in Data-Center
Road to Green Metrics – from the Storage Industry Perspective
Workshop Announcement & Agenda
Post-Silicon Validation Workshop
Post-Si Validation Experience: History, Trends, and Challenges
Directable Functional Exercisers
Lightweight, Scalable Tools for Hardware Validation
Runtime Pipeline Checking: Seatbelts for Your CPU
Post-Silicon Validation of Multicore Chips Using Dynamic Verification
Runtime Validation of Transaction Memory Systems
Engineering Trust with Semantic Guardians
The Challenges of Correlating Silicon and Models in High Variability CMOS Processes
Design Visibility in Post Silicon Verification
GSRC - Quo Vadis?
Chip Life Management Through Sensor and in situ Monitoring of Reliability Degradation
Mutations for Coverage and Fault Tolerance
Architecture Implications of 3D Integration and Other Technologies
A Biologist's Need for Computation -- Agony & Ecstasy
Rethinking Resilience
Sustaining Error Resiliency: The IBM POWER6TM Microprocessor
Virtualization & Machine Learning: A New Approach to Server HA
CRISTA: An Integrated Technique for Voltage-overscaling and Error Resiliency
A Formal Framework for Validating Application-aware Error Detectors
Resilient System Design Theme: Surviving In the Silicon Jungle
The Importance of Test
Exploiting the Synergy Between Fault Tolerance, Manufacturing Test and Debug
CrashTest: Resiliency Analysis Framework
Metrics for Architecture-Level Lifetime Reliability Analysis
Models and Metrics for Test
SymPLFIED: Symbolic Program Level Fault Injection and Error Detection Framework
Reliability Modeling and Simulation for Nanoscale Design
NBTI Induced Performance Degradation in Logic and Memory Circuits: How Effectively Can We Approach a Reliability Solution?
Specification Based Testing vs. Fault Based Testing: Dilemma for Low Cost Testing of Mixed- Signal and RF Circuits
Workloads of the Future
Future Workloads for Designing Future Computers
Print Workload
NERSC Workload Analysis
Where are Internet workloads going?
Workloads of the Future: "Mobility, Community, Serendipity"
Connecting the Unconnected: the networking challenge
Remarks on Workloads of the Future
NVIDIA GPU Computing
GSRC Workshop: Workloads of the Future
High Performance Buildings (Systems) (...and Power...) Challenges for Embedded Systems & Enabling Opprotunities for GSRC
New Automotive DNA
Verification Driven Formal Architecture and Microarchitecture (Requires Windows and IE 6) Slides in PDF
Application-Aware Error Detectors and their Hardware Implementation Slides in PDF
Resilient System Design Theme: Surviving In the Silicon Jungle Slides in PDF
State of the Center Slides in PDF
Application-Aware Error Detectors and their Hardware Implementation
Runtime Validation of Memory Ordering Using Constraint Graph Checking
Analysis and Implementation of Sensors for System-Level Reliability Monitoring
Yield-Centric Design Framework for Low Voltage Robust Systems
StageNet: A Wearout Tolerant CMP System
Resilient Systems Design Thrust - June Research Meeting
Analysis of System-Level Reliability Factors and Implications on Sensor-Based Design
Static Derivation of Application-Aware Error Detectors and their Hardware Implementation
Shielding Against Design Flaws with Field-Repairable Control Logic
Verification-Guided Soft Error Resilience
CRISTA: Voltage Scaling & Critical Path Isolation for Low- Power & Process-Tolerance
Ultra-Low Cost Defect Tolerant Architectures
VIZOR: Virtually Zero Margin RF Using Hot Checking and Real-time Adaptation
Identifying Critical Gates under Circuit Aging
Summary of Current Activities
Low-Cost Test, Diagnosis and Tuning for Adaptive RF Systems (Requires Windows and IE 6) Slides in PDF
Methodologies for Adaptation to Process Variations, Manufacturing Defects, and Transient Errors in Scaled CMOS (Requires Windows and IE 6) Slides in PDF
Bit-Error-Rate Estimation for High-Speed Serial Links (Requires Windows and IE 6) Slides in PDF
CollabRadio: Bio-inspired, Variablity Resistant RF Front End
Imperfection-Immune Carbon Nanotube FET Circuits
Robust Design of DSP Functional Units for Wireless
Towards a Hardware-Software Co-Designed Resilient System
Highlights of the Resilient System Design Theme
The µArchitecture Thrust: What is it, and where is it going
FIRST: Fingerprints In Reliability and Self Test
Modeling Processor Performance for Design Optimization
High-Performance 3D Microarchitecture
Towards an ideal interconnection fabric for many-core chips
Built-In Test, Measurement and Adaptation for Process-Resilient RF Front Ends
Digitally-Assisted Analog Test, Characterization and Tuning for Mixed-Signal Systems
Ultra Low-Cost Defect Protection for Microprocessor Pipelines
Error Resilient System Architecture for Emerging Killer Applications
The Impact of NBTI on the Performance of Combinational and Sequential Circuits
Verification Through the Principle of Least Astonishment
Yield-centric design under process variation and scaled Vdd
Verification-Guided Error Resilience
Body-Bias clustering for post silicon compenstaion of process variation
Buy, Sell, Hold: Online Statistical Timing Analysis for Wearout Detection
Design Modeling for Verification
Panel Discussion Sep 2006 - Austin
Reliable Systems Design Thrust: Key Thrusts Overview
Stress Reduction Cluster
Error Resilient Design Cluster
Failure Modeling Cluster
Novel Research Directions
Resilient System Design Theme
ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon
Concurrent Built-In Signatured Diagnosis and Adaptation for RF/Multi-GHz Systems: BISD
Robust Design of DSP Functional Units for Wireless Communication
Process Variations in Nano-scale Technologies: Failure Analysis, Self-Calibration, Process- Compensation, & Fault Tolerance
Continuous Continuous verification: Correct execution, no matter what
Runtime Functional Validation of Hardware
Robust System Design
A Unified Framework for Hardware and Software Reliability
Verification for Resilience
Monitoring, Diagnosis, and Predictive Framework for System Reliability
Vertically Vertically Integrated Approach to Achieving System-wide Reliability
Design of Error-Resilient CMP Architectures
System-Aware Test and Automatic Diagnosis for Sub-Systems
