Faculty Tasks Students Papers Demos Posters Talks
Adaptive Precision Arithmetic (APA) for Error Tolerant Applications
An efficient Method to Identify Critical Gates under Circuit Aging
An Emulation Platform for Evaluating Thermal and Reliability Effects in CMPs
Analysis on Timing Margining Test for High-Speed Serial Interfaces
Automatable Hazard Checking for Transaction Level Microarchitecture Models
BulletProof Microprocessor Pipelines
Cooperative Hardware-Software Reliability
CRISTA: A Process-Tolerant, Low Voltage Design Methodology using Adaptive Clocking for High-Performance Processors
Design Paradigm for Low-Power, Variation-Resilient Systems using Adaptive Quality Modulation
Digitally-Assisted Analog Testing
Error Resilient System Architecture (ERSA) for Probabilistic Applications
FRiCLe: Field Reparable Control Logic
Inferno: Verification With Transactions
Low-Cost Test of OFDM Transmitter Specifications for QoS (EVM/BER)
Multiprocessor Approach to Error Prevention in Applications
NBTI under Arbitrary Dynamic Temperature Variation
Post Fabrication Adaptation to Process Variations and Manufacturing Defects
PriM: Verification Driven Formal Architecture and Microarchitecture Modeling
Probabilistic Compensation in Digital Filters Using Linearized Checksums
Runtime Validation of Memory Ordering Using Constraint Graph Checking
Self-Healing Emulation on BEE2 System
StageNet: An Adaptive CMP System for Wearout Tolerant Computing
Test Strategy and Yield Analysis for Multi-core systems with Spares
Verification-Guided Error Resilience
VIZOR: Virtually Zero Margin Adaptive RF for Ultra Low Power Wireless Communication
BER Testing for High-Speed Serial Links
Low-cost System-level Testing of Wireless Transceivers
On-Chip Self-Calibration of RF Circuit Using Specification-Driven Built-In Alternate Test
Predicting Mixed-Signal Specifications With Improved Accuracy Using Optimized Signatures
Production Testing Techniques for Ultra Wideband Transceivers
Pseudo-Functional Testing
Runtime Leakage Reduction through Probability-Aware Vt , Tox Assignment and Logic Restructuring