Faculty Tasks Students Papers Demos Posters Talks
Architecture Implications of 3D Integration and Other Technologies
A Biologist's Need for Computation -- Agony & Ecstasy
The Core Theme
TLM Functional Verification and Interface to Metro-II
Pattern Identification and Extraction in Behavioral Synthesis and ASIP Designs
Latency-Insensitive Design and Communication-Synthesis
Communication Modeling for System Level Design
Stochastic Design and Analysis of Networks-on-Chip
Performance, Energy, and Fault-tolerance Issues in NoC Design Slides in PDF
Core Theme Overview and Design Flow
Energy-Aware Design for 1000 Cores: Exploiting VFIs for NoC-Based Systems
MC-Sim: an Efficient Simulation Tool for Heterogeneous Multi-core Systems
MetroSPICE++ Core Update
Synthesis of Reconfigurable High High-Performance Multicore Systems
System-Level Modeling II (Routers)
TLM Verification Tool and Interface to Metro-II
Workloads of the Future
Future Workloads for Designing Future Computers
Print Workload
NERSC Workload Analysis
Where are Internet workloads going?
Workloads of the Future: "Mobility, Community, Serendipity"
Connecting the Unconnected: the networking challenge
Remarks on Workloads of the Future
NVIDIA GPU Computing
GSRC Workshop: Workloads of the Future
High Performance Buildings (Systems) (...and Power...) Challenges for Embedded Systems & Enabling Opprotunities for GSRC
New Automotive DNA
An Extensible Synthesis Approach for Meeting Latency Requirements in Distributed Systems Slides in PDF
Highlights of Core Theme
Highlights of Core Theme Slides in PDF
State of the Center Slides in PDF
An Extensible Synthesis Approach for Meeting Latency Requirements in Distributed Systems
Proposals for Metro II Execution Semantics for Mapping
TLM Generation and Verification and Interface to Metro-II
Hybrid System Simulation and Abstraction: MetroSPICE++
COSI
System-Level Communication Modeling: Integration, Validation, Status
ASPN Simulation and Synthesis
Application Specific Processor Network Synthesis
Communication-Based Design
Correct-by-Construction Methods for Communication-Centric Design
Design of Embedded Networks
MCSim: A Fast Simulation Framework for Communication-Centric Processor Network Exploration
Metro II: Main Features and Progress Update
MetroSPICE++ and ColabRadio: Synergistic Activities
Modeling and Estimation
Modeling On-Chip Communication (Stochastic and Non-stochastic...)
System-Level Interconnect Modeling: Integration, Validation, Status
TLM Verification Tool and its Interface with Metro-II
Synthesis of Application-Specific Multiprocessor Systems (Requires Windows and IE 6) Slides in PDF
High Level CPU Microarchitecture Models Using Kahn Process Networks (Requires Windows and IE 6) Slides in PDF
Statistical Timing and Yield Estimation Based on Realistic Descriptions of Parameter Uncertainty (Requires Windows and IE 6) Slides in PDF
Period Synthesis for Hard Real-time Distributed Automotive Systems (Requires Windows and IE 6) Slides in PDF
Communication-centric SoC Design for Nanoscale Domain (Requires Windows and IE 6) Slides in PDF
Application Specific Processor Synthesis
Lxpilot
MetroII: Main Features and Pre-Alpha Release
Verification of Transaction Level Models
Correct-By-Construction Methods for Communication-Based Design
Hybrid System Simulation: MetroSPICE++
OpenIMPACT -> xPilot Bridge
System-Level Modeling
Metro II
Common Modeling Domain for System Level Design
Architecture Description Language Study
Communication-based Design
Application-Specific Multiprocessor System Synthesis
Synthesis Synthesis techniques for real-time distributed scheduling
Hybrid System Simulation: MetroSPICE++ (and CollabRadio Design Driver)