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Design Technologies for Concurrent Systems

 These are the tasks of the concurrent theme, as set forth in the 2006 GSRC Proposal.

Cluster 1.1.1:   Top-Down Attack
Task 1.1.1.1. -- Explicitly Concurrent Programming Development Environment
PIs: Krste Asanovic, Kurt Keutzer
Task 1.1.1.2. -- Exposure and Exploitation of Coarse-Grain Parallelism in Traditional Programming Models
PI: Wen-mei Hwu
Task 1.1.1.3. -- Robust Thread-level Auto Parallelization
PI: David August
Task 1.1.1.4. -- Harware/Software Suport for Decomposing Single-Threaded Applications into Concurrent Strands
PI: Scott Mahlke
Task 1.1.1.5. -- Streaming Programming Model for Multi-Core
PI: Saman Amarasinghe
Task 1.1.1.6. -- Compositional Verification of Software Components on Multi-Core Chips
PI: Edmund Clarke
Cluster 1.1.2:   Bottom-Up Attack
Task 1.1.2.1. -- RAMP - Research Accelerator for Multiple Processors
PI: John Wawrzynek
Task 1.1.2.2. -- OS Support for Future Heterogeneous Embedded Systems
PIs: Steven Lumetta, Jose (Nacho) Navarro
Task 1.1.2.3. -- Efficient Inter-Thread Communication Mechanisms
PI: Matthew Frank
Task 1.1.2.4. -- Network-Driven Computing
PI: Li-Shiuan Peh
Task 1.1.2.5. -- Hardware and Software Interface for On-chip Parallelism
PI: Margaret Martonosi
Task 1.1.2.6. -- Metamorphosis: A Paradigm for Resilient Concurrency
PI: Mary Jane Irwin
Task 1.1.2.7. -- Design-Aware Verification of Multi-Core Systems
PI: Karem Sakallah

 
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