Faculty Tasks Students Papers Demos Posters Talks
Architecture Implications of 3D Integration and Other Technologies
A Biologist's Need for Computation -- Agony & Ecstasy
Concurrent Systems Theme
A Map Reduce Framework for Programming GPUs
Architectural Support to Eliminate Barriers in Parallel Programming and Automatic Parallelization
Reliability-Aware Design for Multi-Processor Systems on Chip
Workloads of the Future
Future Workloads for Designing Future Computers
Print Workload
NERSC Workload Analysis
Where are Internet workloads going?
Workloads of the Future: "Mobility, Community, Serendipity"
Connecting the Unconnected: the networking challenge
Remarks on Workloads of the Future
NVIDIA GPU Computing
GSRC Workshop: Workloads of the Future
High Performance Buildings (Systems) (...and Power...) Challenges for Embedded Systems & Enabling Opprotunities for GSRC
New Automotive DNA
Concurrent Systems Theme Slides in PDF
Optimization for Highly Parallel Systems Slides in PDF
State of the Center Slides in PDF
Implicitly Parallel Flow -- Thrust Highlights
Concurrent Systems Theme: Natural Programming Models Group
Verification of Transactional Memory and Transactor Concurrent Programs
Concurrent Microarchitecture Thrust Highlights
Networks-on-Chip (NoC) for Concurrent Systems
Parallelism Challenges: Identify vs. Map vs. Manage
A Transactional Memory SAT Solver
Implicitly Parallel Programming Models For Thousand-Core Microprocessors
Parallelism: Identify vs. Map vs. Manage
Vision for the Future of Multi-Core Computing - Panel Discussion
Deep Program Analysis for Coarse-Grained Parallelization (Requires Windows and IE 6) Slides in PDF
Enabling Better Library Parallelization with Function Annotations (Requires Windows and IE 6) Slides in PDF
Exploring Heterogeneous Dynamic Thread Modulation on Chip-multiprocessors (Requires Windows and IE 6) Slides in PDF
Towards the Ideal On-Chip Interconnect Fabric
Towards the Ideal On-Chip Interconnect Fabric (Requires Windows and IE 6) Slides in PDF
A Framework for Implementing Whole Program Optimization within a Production Compiler (Requires Windows and IE 6) Slides in PDF
ViChaR: A Dynamic Virtual Channel Regulator and Unified Buffer Structure for On-Chip Routers (Requires Windows and IE 6) Slides in PDF
Concurrent Systems Theme Meeting
Concurrent Systems Theme: Explicitly Parallel Programming Models Group
Program and Reason about Transactions
Identifying and Extracting Loop Level Parallelism in GP Applications
Implicit Parallel Programming Models?
Automatic Verification Demo
Microarchitecture Group I
Concurrent Theme: 3D & NoC: An Emerging Interconnect Paradigm
Towards the Ideal On-Chip Interconnection Fabric for Many-Core Chips
SMART - Scalable Multicore Architecture with RF and 3D Interconnects
The µArchitecture Thrust: What is it, and where is it going
The Merge Framework: A general purpose architecture based on MapReduce
Making Transactional Memory Practical
Applications Oriented Architecture
Microarchitectural Support for Automatic Parallelization
Extracting Statistical Loop-Level Parallelism from General Purpose Applications
Dynamic Modulation and Management in CMP Systems
Adapting Application Execution to Reduced Processor Availability
Towards a Hardware-Software Co-Designed Resilient System
FIRST: Fingerprints In Reliability and Self Test
Modeling Processor Performance for Design Optimization
High-Performance 3D Microarchitecture
Towards an ideal interconnection fabric for many-core chips
Panel Discussion Sep 2006 - Hwu
Concurrent Application Mapping onto Multiprocessor SOCs
StreamIt - Natural Expression of Parallelism in Stream Programs
Transactors
Microarchitecture and OS for Concurrency the "bottom-up" portion of the new Concurrent Systems Theme
Mapping Parallel Applications to Heterogeneous Resources
Design-Aware Verification of Multi-Core Systems
Architectural Support for Speculative Dynamic Dataflow