Faculty
Tasks
Students
Papers
Demos
Posters
Talks
| Design Technologies for Concurrent Systems |
| |
- Virtual Circuit Tree Multicasting: A Case for Hardware Multicast Support,
-
- Circuit-Switched Coherence,
-
- GPU Acceleration of Cutoff Pair Potentials for Molecular Modeling Applications,
-
- A Study on Monetary Cost Analysis for Product Line Architectures,
-
- Logical Reliability of Interacting Real-Time Tasks,
-
- CUBA: An Architecture for Efficient CPU/Co-processor Data Communication,
-
- MCUDA: An Efficient Implementation of CUDA Kernels on Multi-cores,
-
- Accelerating Advanced MRI Reconstructions on GPUs,
-
- How GPUs Can Improve the Quality of Magnetic Resonance Imaging,
-
- A Helper Thread Based EDP Reduction Scheme for Adapting Application Execution in CMPs,
-
- How GPUs Can Improve the Quality of Magnetic Resonance Imaging,
-
- A 4.6Tbits/s 3.6GHz Single-cycle NoC Router with a Novel Switch Allocator in 65nm CMOS,
-
- Uncovering Hidden Loop Level Parallelism in Sequential Applications,
-
- Program Optimization Strategies for Data-Parallel Many-Core Processors,
-
- How GPUs Can Improve the Quality of Magnetic Resonance Imaging,
-
- NoC Prototyping Using FPGAs: Challenges and Promising Results in NoC Prototyping Using FPGAs,
-
- Sub-RISC Processors,
-
- A Decomposition-based Constraint Optimization Approach for Statically Scheduling Task Graphs with Communication Delays to Multiprocessors,
-
- Sketching Stencils,
- Armando Solar-Lezama, Gilad Arnold, Liviu Tancau, Rastislav Bodik, Vijay Saraswat, and Sanjit A. Seshia.
- Virtual Channels Planning for Networks-on-Chip,
- T.-C. Huang, U. Y. Ogras, R. Marculescu
- Analytical Router Modeling for Networks-on-Chip Performance Analysis,
- U. Y. Ogras, R. Marculescu
| |
|
|
|
