The Platform Architectures theme

Architecture and Synthesis Support for Accelerator-Rich CMPs
Running 1000 Threads on a General-Purpose Multi-Core
Network-Driven Chips
Platform Architectures Theme Overview
GSRC State of the Center
Characterizing and Improving Last-level Cache Management using Signature-based and Prefetch-aware Approaches
Memory Scheduling to Enhance Both System Throughput and Fairness
Tightly Coupled Accelerators using Intel Ž QuickAssist QPI-FPGA Technology
Blue Gene Active Storage
Packing in More Bits
Liquid Metal Program
Flexible Accelerator Architectures
HW/SW Interface
Exascale Architectural Exploration
Early Chip Physical Planning for 3D Applications
SoC Design
Using DRAM Instead of Disks for Datacenter Storage: RAMCloud
Thread Cluster Memory Scheduling
The Watson Machine: Today and Tomorrow
Key Technology Challenges for Next Decade
State of the Center
Hardware-Software Interface Design Issues for Parallelism and Power-Efficiency
Architecture Support for Customization and Specialization

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