The Platform Architectures theme

Fine grained accelerator integration using 3D
Power-Performance Modeling for General-Purpose and Accelerator-Based Systems
Thread Cluster Memory Scheduling
Improving Cache Performance Using Victim Tag Stores
Integrated Framework Combining Virtual Platform and NoC Synthesis for Heterogeneous Systems-on-Chip
Supervised Design Space Exploration of Accelerators and Cores in Heterogeneous SoCs
Row Buffer Locality-Aware Hybrid Memory Caching Policies
TLM Platform for Heterogeneous System-on-Chip Integration
Contracts for Correct Composition and System-Level Design of Analog and Mixed-Signal Circuits
Towards the Ideal On-chip Fabric for 1-to-Many and Many-to-1 Communication
A Design Framework for Distributed Power Management of Heterogeneous Systems-on-Chip
Research on Network-on-Chip Router Modeling
Energy Benefits of Power Gating on Memory Misses in Multi-Core Systems
A Case for Locality-Aware Task Management on Many-Core Processors

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