Architecture Implications of 3D Integration and Other Technologies
A Biologist's Need for Computation -- Agony & Ecstasy
Alternative Computational Models
Oscillator Networks, their Properties and Potential Applications
Networked Computation
Exploring Unreliable Technology Scaling for High Performance Systems
Coding for High-Defect Fabrics
Imperfection-Immune CNFET Circuits
Stochastic Communication
Concurrent Systems Theme
A Map Reduce Framework for Programming GPUs
Architectural Support to Eliminate Barriers in Parallel Programming and Automatic Parallelization
Reliability-Aware Design for Multi-Processor Systems on Chip
The Core Theme
TLM Functional Verification and Interface to Metro-II
Pattern Identification and Extraction in Behavioral Synthesis and ASIP Designs
Latency-Insensitive Design and Communication-Synthesis
Communication Modeling for System Level Design
Stochastic Design and Analysis of Networks-on-Chip
Rethinking Resilience
Sustaining Error Resiliency: The IBM POWER6TM Microprocessor
Virtualization & Machine Learning: A New Approach to Server HA
CRISTA: An Integrated Technique for Voltage-overscaling and Error Resiliency
A Formal Framework for Validating Application-aware Error Detectors
GSRC Design Drivers
Performance, Energy, and Fault-tolerance Issues in NoC Design Slides in PDF
Collaborative Radio Project Update
Imperfection-Immune Carbon Nanotube FET Circuits
Perturbation Based Computing
Stochastic Sensor Network-on-a-Chip
Using Defect-Map Knowledge for More Efficient Coding
Core Theme Overview and Design Flow
Energy-Aware Design for 1000 Cores: Exploiting VFIs for NoC-Based Systems
MC-Sim: an Efficient Simulation Tool for Heterogeneous Multi-core Systems
MetroSPICE++ Core Update
Synthesis of Reconfigurable High High-Performance Multicore Systems
System-Level Modeling II (Routers)
TLM Verification Tool and Interface to Metro-II
Modeling and Metrics Initiative: In Search of Common Ground
Resilient System Design Theme: Surviving In the Silicon Jungle
The Importance of Test
Exploiting the Synergy Between Fault Tolerance, Manufacturing Test and Debug
CrashTest: Resiliency Analysis Framework
Metrics for Architecture-Level Lifetime Reliability Analysis
Models and Metrics for Test
SymPLFIED: Symbolic Program Level Fault Injection and Error Detection Framework
Reliability Modeling and Simulation for Nanoscale Design
NBTI Induced Performance Degradation in Logic and Memory Circuits: How Effectively Can We Approach a Reliability Solution?
Specification Based Testing vs. Fault Based Testing: Dilemma for Low Cost Testing of Mixed- Signal and RF Circuits
Workloads of the Future
Future Workloads for Designing Future Computers
Print Workload
NERSC Workload Analysis
Where are Internet workloads going?
Workloads of the Future: "Mobility, Community, Serendipity"
Connecting the Unconnected: the networking challenge
Remarks on Workloads of the Future
NVIDIA GPU Computing
GSRC Workshop: Workloads of the Future
High Performance Buildings (Systems) (...and Power...) Challenges for Embedded Systems & Enabling Opprotunities for GSRC
New Automotive DNA
Theoretical Foundations (Alternatives subtheme)
Communication Fabrics
Verification Driven Formal Architecture and Microarchitecture (Requires Windows and IE 6) Slides in PDF
Alternative Computational Models Slides in PDF
An Extensible Synthesis Approach for Meeting Latency Requirements in Distributed Systems Slides in PDF
Application-Aware Error Detectors and their Hardware Implementation Slides in PDF
Automated Design of Misalignment-Immune CNT Circuits Slides in PDF
Concurrent Systems Theme Slides in PDF
GSRC Design Drivers Slides in PDF
Highlights of Core Theme
Highlights of Core Theme Slides in PDF
Optimization for Highly Parallel Systems Slides in PDF
RAMP Blue: A Message-Passing Many-Core System in FPGAs Slides in PDF
Resilient System Design Theme: Surviving In the Silicon Jungle Slides in PDF
State of the Center Slides in PDF
An Extensible Synthesis Approach for Meeting Latency Requirements in Distributed Systems
Application-Aware Error Detectors and their Hardware Implementation
Automated Design of Misalignment-Immune CNT Circuits
RAMP Blue: A Message-Passing Many-Core System in FPGAs
Proposals for Metro II Execution Semantics for Mapping
Runtime Validation of Memory Ordering Using Constraint Graph Checking
Analysis and Implementation of Sensors for System-Level Reliability Monitoring
Implicitly Parallel Flow -- Thrust Highlights
TLM Generation and Verification and Interface to Metro-II
Concurrent Systems Theme: Natural Programming Models Group
Hybrid System Simulation and Abstraction: MetroSPICE++
Yield-Centric Design Framework for Low Voltage Robust Systems
COSI
StageNet: A Wearout Tolerant CMP System
Verification of Transactional Memory and Transactor Concurrent Programs
Concurrent Microarchitecture Thrust Highlights
Design Principles for Perturbation Based Computing
System-Level Communication Modeling: Integration, Validation, Status
ASPN Simulation and Synthesis
Networks-on-Chip (NoC) for Concurrent Systems
Sensor Network-Inspired Energy Efficient Design
Parallelism Challenges: Identify vs. Map vs. Manage
Theoretical Foundations: (Alternatives subtheme)
A Transactional Memory SAT Solver
Implicitly Parallel Programming Models For Thousand-Core Microprocessors
Parallelism: Identify vs. Map vs. Manage
Vision for the Future of Multi-Core Computing - Panel Discussion
Resilient Systems Design Thrust - June Research Meeting
Analysis of System-Level Reliability Factors and Implications on Sensor-Based Design
Static Derivation of Application-Aware Error Detectors and their Hardware Implementation
Shielding Against Design Flaws with Field-Repairable Control Logic
Verification-Guided Soft Error Resilience
CRISTA: Voltage Scaling & Critical Path Isolation for Low- Power & Process-Tolerance
Ultra-Low Cost Defect Tolerant Architectures
VIZOR: Virtually Zero Margin RF Using Hot Checking and Real-time Adaptation
Identifying Critical Gates under Circuit Aging
Summary of Current Activities
Alternative Challenges
Application Specific Processor Network Synthesis
Coding Techniques for Future Nano-circuits
Communication-Based Design
Correct-by-Construction Methods for Communication-Centric Design
Design of Embedded Networks
Distributed synchronization/communication protocols for dense networks
Imperfection Immune CMFET Circuits
Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-Transition Equations
MCSim: A Fast Simulation Framework for Communication-Centric Processor Network Exploration
Metro II: Main Features and Progress Update
MetroSPICE++ and ColabRadio: Synergistic Activities
Modeling and Estimation
Modeling On-Chip Communication (Stochastic and Non-stochastic...)
Network-Inspired System Design
On-Chip Stochastic Communication: Modeling, Analysis and Optimization
Progress in CollabRadio Project
Statistical Sensor Network-On-Chip
System-Level Interconnect Modeling: Integration, Validation, Status
TLM Verification Tool and its Interface with Metro-II
Synthesis of Application-Specific Multiprocessor Systems (Requires Windows and IE 6) Slides in PDF
High Level CPU Microarchitecture Models Using Kahn Process Networks (Requires Windows and IE 6) Slides in PDF
Statistical Timing and Yield Estimation Based on Realistic Descriptions of Parameter Uncertainty (Requires Windows and IE 6) Slides in PDF
Low-Cost Test, Diagnosis and Tuning for Adaptive RF Systems (Requires Windows and IE 6) Slides in PDF
Deep Program Analysis for Coarse-Grained Parallelization (Requires Windows and IE 6) Slides in PDF
Enabling Better Library Parallelization with Function Annotations (Requires Windows and IE 6) Slides in PDF
Exploring Heterogeneous Dynamic Thread Modulation on Chip-multiprocessors (Requires Windows and IE 6) Slides in PDF
Towards the Ideal On-Chip Interconnect Fabric
Towards the Ideal On-Chip Interconnect Fabric (Requires Windows and IE 6) Slides in PDF
Methodologies for Adaptation to Process Variations, Manufacturing Defects, and Transient Errors in Scaled CMOS (Requires Windows and IE 6) Slides in PDF
Period Synthesis for Hard Real-time Distributed Automotive Systems (Requires Windows and IE 6) Slides in PDF
Bit-Error-Rate Estimation for High-Speed Serial Links (Requires Windows and IE 6) Slides in PDF
A Framework for Implementing Whole Program Optimization within a Production Compiler (Requires Windows and IE 6) Slides in PDF
ViChaR: A Dynamic Virtual Channel Regulator and Unified Buffer Structure for On-Chip Routers (Requires Windows and IE 6) Slides in PDF
Communication-centric SoC Design for Nanoscale Domain (Requires Windows and IE 6) Slides in PDF
Generation of Efficient Codes for Realizing Boolean Functions in Nanotechnologies (Requires Windows and IE 6) Slides in PDF
"Barriers" and Opportunities for Platform Microarchitecture 2015
A Tribute to Richard Newton / GSRC at a Glance