| | GSRC Student Profile:
Research Overview: Network-on-Chip: A system-level approach to variation and fault tolerance.
With reduction in transistor feature sizes and increases in parametric
and functional variability, it may no longer be possible to manage die
yields statically. Designers and engineers currently employ a range
of methods to intelligently ``over-engineer'' circuits by widening
margins, not just to combat noise, power voltage and current
fluctuations, but also variations inherent in semiconductor processing
steps. This ``over-engineering'' comes at the cost of wasted die area,
power, and performance.
Current trends in VLSI design in several application domains point to
the new architecture paradigm: multiple processor cores composed with
network-on-chip (NoC). The NoC in the modern design methodology
creates regularity in communication and computation blocks that opens
the door to high-level run-time techniques that mitigate the effects
of performance variability, permanent and transient faults. Run-time
adaptive process mapping and routing can minimize the impact of faults
and performance variability on the system, rather than masking the
problems by ``over-engineering.'' By raising the level of abstraction,
these high level run-time techniques (akin to operating system
resource management) provide a consistent, uniform way to deal with
on/off die static and dynamic performance variations as well as both
permanent and transient faults.
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