| | GSRC Student Profile:
Research Overview: Architecture Designs and Compiler Optimizations for Chip Multiple Processors
Chip Multiple Processors (CMPs) have become the trend of future computer architecture. However, many problems about how to utilize CMPs in most effective way are still open. This brings us new opportunities to develop new architecture designs and apply compiler optimizations so that good tradeoffs can be made among power, performance and reliability.
Right now, I am working on two specifical problems. The first problem is how to find the optimal scheduling for CMPs in the exploration space of number of cores, number of threads and different frequency/voltage levels. The second problem is how a global manager using different hardware counters can interact with the software and improve the execution on CMPs.
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