GSRC theme: resilient
Expected graduation: May, 2012
Research Overview: Verification-guided Error Resilience
Our research focuses on combining formal and simulation techniques to estimate circuit vulnerabilities and provide error resilience. Current research includes providing a complete methodology to soft error vulnerabilities estimation by an efficient and accurate circuit simulation and a system level analysis; developing a theory of mutations for analyzing coverage for fault tolerant circuits and automatically strengthening specifications in the case of low coverage.
