University of California, Berkeley
Advisor: Jan Rabaey
GSRC theme: alternative
Expected graduation: May, 2010
Research Overview: Asynchronous Computing in Pass Transistor Logic
Sense amplifier-based pass-transistor logic style (SAPTL) is a promising candidate to realize ultra low energy computation without soliciting sub-threshold operation and sacrificing performance. The asynchronous self-timed methodology can potentially apply to SAPTL architecture with very little overhead to further enhance speed performance as well as reliability. The overall research focuses on architectural optimization and design strategy for self-timed SAPTL in system level. The signal processing prototypes implemented by proposed design methodology and traditional CMOS flow will be used for final performance comparison
