GSRC Student Profile:
Research Overview: Single and Multi-CPU Performance Modeling for Embedded Systems
This work focuses on the modeling of the performance of software executing on embedded processors in the context of a heterogeneous
multi-processor system on chip in a more scalable manner than current approaches. It contains three major parts. The first part describes different levels of abstraction for modeling such systems
and how their speed and accuracy trade-offs relate. The second part presents our modeling microarchitectural performance of a single
processor in an intuitive and retargetable manner using a high-level description in Kahn Process Networks. The final portion explores
multi-processor modeling at different levels of abstraction using both co-simulation and performance backwards annotation.
The first portion of this work defines different levels of abstraction for performance of modeling microprocessors and hardware in general. The levels from cycle accurate models and below (e.g.
signal level models) are clearly defined, but levels above cycle-accurate aren't that well defined. Transaction Level Modeling (TLM) represents above-rtl modeling with communication being implemented as function calls, but the definitions beyond this are still forming and are unclear. This work further refines the definition of this, and also presents a framework for comparing models of embedded software performance.
Our microarchitectural models use the Kahn Process Network formalism with the FIFO's kept at a constant length to represent delays. These
models execute on traces generated by a functional ISS (Instruction Set Simulator) and only model instruction timings and operand dependencies making them easier to both retarget and perform
microarchitectural exploration than traditional techniques. StrongARM and XScale microprocessors accompanying memory models developed with methodology are presented.
For the multi-processor portion of the work we are examining: co-simulation, mixed level modeling and performance backwards annotation. Performance backwards annotation writes the execution
times of code executing on the target model back at to the functional model at a user-specified level of granularity. Such models are more accurate than coarse-grained instruction-level
models, yet will be much faster than co-simulating with low-level models. These techniques are applied to a heterogeneous multiprocessor from Infineon intended for software defined radio, and is compared to its cycle-level virtual prototype in terms of speed and accuracy.
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