| | GSRC Student Profile:
Research Overview: Low power and robust design for nanometer technologies
Process variations along with higher levels of integration can lead to large spread in circuit delay, power, and robustness across different dies. Parameter variations adversely affect minimum geometry circuits such as SRAM cells leading to parametric failures, while logic circuits may experience delay failures or excessive leakage. Increasing power density due to faster clock, leakage and high device integration causes die overheating as the cooling capacity of the package is limited.
My research is primarily focussed on design of robust, low power and high performance digital circuits, fault tolerant design and online test. Scaling of technology is also associated with subtle manufacturing defects and new fault mechanisms. I am also investigating design-for-test techniques to reduce test cost (test time, test power, test patterns etc) and attain good test coverage.
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