| | GSRC Student Profile:
Research Overview: Novel Networked Models for Error-Tolerant Computation
Traditional approach to error-tolerant computing in the nanometer CMOS era usually involve some form of redundant computation that counters the benefits of aggressive technology scaling. A networked model of computation allows us to exploit redundancy already present in many applications. The stochastic sensor network-on-chip (SNOC) design implements theoretically optimally mechanisms to overcome computational errors in certain applications. A SNOC-based PN acquisition offers up to 40% savings in power (through error-prone voltage overscaling).
Our current research efforts target development of general SNOC designs and extending this design philosophy to more general application classes. Presently, the SNOC uses a central fusion block that poses a single point-of-failure. We seek to design and implement decentralized fusion architectures that will additionally alleviate problems associated with long-range communication. The other component of our research is to extend the applicability of SNOC designs for more general applicaitons. Currently, this design is applicable for computations that can be decomposed in a statistically similar fashion (polyphase implementation of PN acquisition, for example).
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