| | GSRC Student Profile:
Research Overview: Fault-tolerant Architectures
With the shrinking feature sizes in the upcoming semiconductor technology generations, the reliability of the individual transistor devices is on a decline. This would have a direct impact on the operational life of a semiconductor circuit. Therefore, looking forward to the design of many-core chips, with billions of transistors, fault-tolerance would be a necessity.
The challenge of fault-tolerance can be broken down into three parts:
1) Detection of failure(s)
2) Diagnosis of the cause
3) Reconfiguration of the system
In the recent past I have worked on the first two parts of this problem, i.e. detection and diagnosis. My current research focus is on the third aspect: system reconfiguration for maximizing the throughput. Within this, I am investigating the architectural techniques for reconfiguration and studying trade-offs to ascertain the correct granularity for the same.
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