| | GSRC Student Profile:
Research Overview: Novel Low Power Inteconnect Design
On chip interconnect design is one of the hottest research areas because of the impact of those interconnects on the overall performance of circuits. Ideally, one would want interconnects to be fast, lossless, and low power.
Traditional interconnect modeling assumes a distributed RC model of an interconnect. Due to the quadratic relation between delay and interconnect length, optimal repeater insertion is used as a technique to optimize for delay. The main drawback of this approach is the fact that the inserted repeaters are sized up repeaters that are power hungry.
The idea behind our design is to ensure the propagation of data between the driver and the receiver through capacitive charge transfer along the direct path between them. In other words, the repeaters present in the traditional design are substituted by capacitors, the presence of which requires modifying interconnect layouts to ensure the creation of the desired capacitances. With the proper choices of the needed number of these capacitances, their locations, and their ratios to the bulk capacitances, our design has resulted in power savings of around 70% as compared to traditional designs at comparable delays.
The next goals of our research are to expand the model to take coupling capacitances into consideration, to take process variations into account, and to apply stochastic optimization to determine the optimal circuit design parameters.
| |
