GSRC Student Profile:
Research Overview: Software / Hardware Co-Design for Efficient Task Scheduling on Heterogeneous Systems
Adding more cores to the microprocessor poses new challenges on both software and hardware. The sheer amount of scale would aggravate the overhead in maintaining the parallelism, and enforcing locality in this environment would be challenging. To make things worse, energy efficiency could call for a heterogeneous configuration. For many-core processors to be successful, we need a holistic approach that addresses these problems altogether.
By employing the co-design approach, we aim to bring the current software / hardware efficiency to a whole new level. For the software scheduler, the key is to utilize the existing and proposed information from high-level programming models such as Intel TBB and OpenCL. This information includes task affinity, producer consumer dependencies, and explicit communication patterns. We would then revisit the hardware to determine what new mechanisms for communication, locality management, and performance could improve on the schedulers' efficiency.
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