GSRC Student Profile:
Research Overview: Reliable Network-on-Chip (NoC), NoC Correctness
Network on Chip Correctness
Modern processors are rapidly shifting towards complex chip multi-processor designs, comprising several processor cores communicating via a network-on-chip (NoC). As a side-effect of this trend, ensuring their correctness has become increasingly problematic. In particular, the network-on-chip often includes complex features and components to support the required communication bandwidth among the nodes in the system. In this landscape, it is no wonder that design errors in the NoC may go undetected and escape into the final silicon, with potential detrimental impact on the overall system. In this project, I developed novel approaches based on pre-silicon and runtime verification, to ensure NoC correctness under all execution scenarios. This work has been published in ICCD 2011 and MICRO 2011.
Resilient Network on Chip
Networks-on-chip are becoming more susceptible to failure as aggressively scaled transistors become vulnerable to silicon wear-out. The goal of this project is to ensure correct operation of on-chip interconnects in face of in-field permanent failures. To this end, I have developed novel techniques to accurately diagnose the fault site and reconfigure the system to work around faults, providing graceful performance degradation.
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