GSRC Student Profile:
Research Overview: Algorithmic Noise Tolerance for FEC Decoders
With the increased demand for high data rates and low bit error rate communication, more sophisticated coding schemes are being used. Viterbi, Turbo, and LDPC decoders constitute the major part of error correction used in current communication systems. With the demand for better performance over low quality channels, the complexity of these decoders entails a tremendous increase in the consumed power.
We will investigate the application of algorithmic noise tolerance (ANT) to Viterbi decoders and the power savings that can be achieved. Another factor we will consider with the state of the art decoders is their reliability as the transistor size is shrunk down with each technology node. Therefore, we will also conduct a study of ANT schemes for Viterbi decoder to maintain its reliability in the presence of process variations.
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