GSRC Student Profile:
Peter Lisherness
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University of California, Santa Barbara
Advisor: Tim Cheng
GSRC theme: viability
Expected graduation: Jun, 2012 |
Research Overview: Models and Coverage Metrics for Effective System-Level Validation
The cost of post-silicon validation continues to rise for SoC devices, partially due to a lack of quality metrics for post-silicon validation tests, which results in an increasing reliance on engineers’ intuition or empirical data to guide validation test selection and development. While in principle significant synergy exists among pre-silicon verification, post-silicon validation, and manufacturing testing, their respective tests are seldom shared. It should be highly beneficial for overall product cost and time-to-market reduction to explore the opportunities for leveraging the efforts, knowledge, and tests of pre-silicon verification and testing for post-silicon validation.
We are currently developing error models and coverage metrics in the context of post-silicon validation, which can then be used to evaluate functional tests derived from the application environment. These models and metrics are being designed to meet three requirements: (1) they must accurately reflect the quality of those tests used for post-silicon validation, (2) they can be computed efficiently, and (3) they should offer information to guide-structured Design for Debug (DfD) solutions.
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