Nilanjan Banerjee
	nbanerje@purdue.edu Purdue University Advisor: Kaushik Roy GSRC theme:  resilient Expected graduation:  May, 2008

Research Overview:  Low Power Variation Tolerant System/Circuit Design

Designing Circuit/System Level Techniques for Low Power : Involves development of efficient design techniques at both the circuit and the system level to reduce the standby and active leakage power along with switching power, while maintaining the system performance.

Estimation and Compensation Techniques for Process Parameter Variations Involves design of test structures for determination and separation of various components of inter-die and intra-die process variations. Circuit/System compensation techniques for reducing these variation effects and preserve the design functionality are also being developed.

Fault-tolerant Execution Cores: Development of the low-cost fault-tolerant execution units (adders/multipliers)