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Research Overview: Parallelizing Implicitly Parallel Programs on Commodity Multicore Systems
Multicore designs have emerged as the mainstream design paradigm for the microprocessor
industry. Unfortunately, providing multiple cores does not directly translate into
performance for most applications. The industry has already fallen short of
the decades-old performance trend of doubling performance every 18 months. An
attractive approach for exploiting multiple cores is to rely on tools, both compilers
and runtime optimizers, to automatically extract threads from sequential, but implicitly parallel applications. However, despite decades of research on automatic parallelization, most techniques
are only effective in the scientific and data parallel domains where array dominated
codes can be precisely analyzed by the compiler. Thread-level speculation offers
the opportunity to expand parallelization to general-purpose programs, but at
the cost of expensive hardware support.
In this work, we focus on providing low-overhead
software support for exploiting speculative parallelism. We propose
STMlite, a light-weight software transactional memory model that is customized to
facilitate profile-guided automatic loop parallelization.
STMlite eliminates a considerable amount of checking and locking overhead in
conventional software transactional memory models by decoupling the commit phase
from main transaction execution. STMlite enables stylized automatic parallelization
of sequential applications to extract meaningful performance gains on commodity
multicore hardware. Furthermore, STMlite efficiently supports the execution of explicitly
parallelized transactional applications in comparison to existing software solutions.
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