| | GSRC Student Profile:
Research Overview: Application Specific Processor Network Synthesis
Given an application and a library of core processors (both hard cores and customizable processors), un-core components (memories) and custom hardware blocks, synthesize a processor "netlist" to optimize a certain objective (timing/area/power) subject to certain constraints (timing/power/area).
Currenty, working on
a) Synthesizing a customized memory hierarchy for a given mapping of an application to a set of processors to minimize energy subject to timing constraints.
b) Synthesize a netlist of processors from a given library of heterogeneous processors with/without resource constraints to minimize latency
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