| | GSRC Student Profile:
Research Overview: Technology & Design Infrastructure for High Performance Three-Dimensional (3-D) ICs
To avoid the disadvantages of feature size scaling, 3D-IC is a promising technique to enable the increase of chip complexity.
My current research topic is to develop a placement algorithm for 3D-ICs. The problem is to minimize the total wire length with the non-overlap constraints and through-the-silicon via (TS via) density constraints. Non-linear programming methods will be used to solve the problem.
And I am also work on the extension of OpenAccess for 3D-ICs and, the integration of a tool chain for 3D physical design flow.
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