| | GSRC Student Profile:
Research Overview: Using Higher-Level Hardware Design Models in Existing RTL Based Design Flows
There is a growing gap between the size of designs made possible by
Moore's law increases, and size of designs that engineers actually
have the ability to efficiently design and verify. Present design
methodologies either start with an algorithmic model, and attempt to
refine it down to hardware, or start with an RTL design, and attempt
to verify it. This leads to a ``meet in the middle problem'' which is
presently bridged by skilled human intervention.
We propose a new refinement methodology called PRIM (PRInceton
Models).PRIM includes both an architectural (algorithmic) model based
on atomic transactions, which we believe provides the most natural way
to describe concurrency. Importantly, PRIM also contains a
micro-architectural (timed, resource constrained) model that can be
both automatically related to the architecture, and automatically
synthesized into RTL, providing the missing link between architecture
and implementation.
My work helps to develop and implement
this framework. In particular, I am developing the
PRIMVerilog language, and exploring the possibilities it allows for reliable
and provable synthesis to hardware.
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