GSRC Student Profile:
Research Overview: OMNI : Ordered Mesh Network Interconnection for Multicore Processors
Research in the area of on-chip networks is reaching a critical point. New technologies and protocols need to be developed for continued growth. With the increasing number of cores within a CMP, a bus will suffer scalability limits.
The research, design, and development of an ordered mesh network interconnect is of utmost significance because it satisfies the latency, bandwidth and power requirements.
The network itself is used to maintain sequential consistency, simplifying the cores and making the interface smarter.
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