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GSRC Student Profile:

Karthik V Aadithya

aadithya@berkeley.edu

University of California, Berkeley
Advisor: Jaijeet Roychowdhury

GSRC theme:  alternatives
Expected graduation:  Dec, 2014

Research Overview:  DAE2FSM: A Fully Automated Technique for Generating Finite State Machine Abstractions for Digital, Analog, and Mixed-Signal Circuits

In this project, we consider the problem of automatically generating discrete-time abstractions for digital, analog, and mixed-signal circuits. Specifically, we have developed a tool (called DAE2FSM) that takes as input a transistor level description of a circuit (e.g., a SPICE netlist), and produces as output a Finite State Machine (FSM) abstraction that accurately reflects the circuit dynamics under both ideal and non-ideal operating conditions. DAE2FSM thereby enables highly efficient, symbol-level simulation of hardware modules, which is a key requirement in the design of many digital/analog/mixed-signal sub-systems (e.g., high-speed communication links).