Citation
Andrey Zykov, Gustavo de Veciana. "Exploring Density-Reliability Tradeoffs on Nanoscale Substrates: When do smaller less reliable devices make sense?". The 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'08), September, 2008.

Abstract
It is widely recognized that device and interconnect fabrics at the nanoscale will be characterized by an increased susceptibility to transient faults. This appears to be intrinsic to nanoscale regimes and fundamentally limits the eventual benefits of the increased device density, i.e., the overheads associated with achieving fault-tolerance may counter the benefits of increased device density. density-reliability tradeoff. At the same time, as devices scale down one can expect a higher proportion of area to be associated with interconnection, i.e., area is wire dominated. This paper theoretically explores density-reliability tradeoffs in wire dominated integrated systems. We derive an area scaling model based on simple assumptions capturing the salient features of hierarchical design for high performance systems. We then evaluate overheads associated with using basic fault-tolerance techniques at different levels of the design hierarchy. This, albeit simplified model, allows us to tackle several interesting questions: When does it make sense to use smaller less reliable devices? At what scale of the design hierarchy should fault tolerance be applied in high performance integrated systems? Our analysis reveals two critical parameters, the technology and design scaling factors, which are key to predicting the reliability requirements for emerging technologies if traditional hierarchical design continues to be used.

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Citation formats

• HTML

  Andrey Zykov, Gustavo de Veciana. <a
  href="http://www.gigascale.org/pubs/1337.html">Exploring
  Density-Reliability Tradeoffs on Nanoscale Substrates: When
  do smaller less reliable devices make sense?</a>, The
  23rd IEEE International Symposium on Defect and Fault
  Tolerance in VLSI Systems (DFT'08), September, 2008.

• Plain text

  Andrey Zykov, Gustavo de Veciana. "Exploring
  Density-Reliability Tradeoffs on Nanoscale Substrates: When
  do smaller less reliable devices make sense?". The 23rd IEEE
  International Symposium on Defect and Fault Tolerance in
  VLSI Systems (DFT'08), September, 2008.

• BibTeX

  @inproceedings{ZykovdeVeciana08_ExploringDensityReliabilityTradeoffsOnNanoscaleSubstrates,
      author = {Andrey Zykov and Gustavo de Veciana},
      title = {Exploring Density-Reliability Tradeoffs on
                Nanoscale Substrates: When do smaller less
                reliable devices make sense?},
      booktitle = {The 23rd IEEE International Symposium on Defect
                and Fault Tolerance in VLSI Systems (DFT'08)},
      month = {September},
      year = {2008},
      abstract = {It is widely recognized that device and
                interconnect fabrics at the nanoscale will be
                characterized by an increased susceptibility to
                transient faults. This appears to be intrinsic to
                nanoscale regimes and fundamentally limits the
                eventual benefits of the increased device density,
                i.e., the overheads associated with achieving
                fault-tolerance may counter the benefits of
                increased device density. density-reliability
                tradeoff. At the same time, as devices scale down
                one can expect a higher proportion of area to be
                associated with interconnection, i.e., area is
                wire dominated. This paper theoretically explores
                density-reliability tradeoffs in wire dominated
                integrated systems. We derive an area scaling
                model based on simple assumptions capturing the
                salient features of hierarchical design for high
                performance systems. We then evaluate overheads
                associated with using basic fault-tolerance
                techniques at different levels of the design
                hierarchy. This, albeit simplified model, allows
                us to tackle several interesting questions: When
                does it make sense to use smaller less reliable
                devices? At what scale of the design hierarchy
                should fault tolerance be applied in high
                performance integrated systems? Our analysis
                reveals two critical parameters, the technology
                and design scaling factors, which are key to
                predicting the reliability requirements for
                emerging technologies if traditional hierarchical
                design continues to be used.},
      URL = {http://www.gigascale.org/pubs/1337.html}
  }
  

Posted by Andrey Zykov on 26 Jul 2008..

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