Citation
Bin Li, Li-Shiuan Peh, Priyadarsan Patra. "Impact of Process and Temperature Variations on Network-on-Chip Design Exploration". IEEE International Symposium on Networks-on-Chip, April, 2008.

Abstract
With the continuing scaling of CMOS technologies, process variation is becoming a key factor highly impacting system-level power and temperature. Traditional methods of assuming a uniform temperature and no process variation can lead to gross inaccuracies even for system-level design, thus it is critical to consider the effects of process variation and temperature variation during early design exploration. In this paper, we describe the implementation of an architecture-level early-stage design space exploration tool that incorporates the effect of process and temperature variation for Network-on-chips(NoC). The tool is used to study the impact of process and temperature variations on power and energy-delay-product-per-flit metrics for different NoC architectures, and our simulation results show that design choices are influenced by the effects of process and temperature variation, thus demonstrating the importance of considering, and enabling the high-level impact analysis of process and temperature variation early in the design flow.

Electronic downloads
Confidential. This publication has been marked by the author for GSRC-only distribution, so electronic downloads are not available without logging in.

Citation formats

• HTML

  Bin Li, Li-Shiuan Peh, Priyadarsan Patra. <a
  href="http://www.gigascale.org/pubs/1288.html">Impact
  of Process and Temperature Variations on Network-on-Chip
  Design Exploration</a>, IEEE International Symposium
  on Networks-on-Chip, April, 2008.

• Plain text

  Bin Li, Li-Shiuan Peh, Priyadarsan Patra. "Impact of Process
  and Temperature Variations on Network-on-Chip Design
  Exploration". IEEE International Symposium on
  Networks-on-Chip, April, 2008.

• BibTeX

  @inproceedings{LiPehPatra08_ImpactOfProcessTemperatureVariationsOnNetworkonChip,
      author = {Bin Li and Li-Shiuan Peh and Priyadarsan Patra},
      title = {Impact of Process and Temperature Variations on
                Network-on-Chip Design Exploration},
      booktitle = {IEEE International Symposium on Networks-on-Chip},
      month = {April},
      year = {2008},
      abstract = {With the continuing scaling of CMOS technologies,
                process variation is becoming a key factor highly
                impacting system-level power and temperature.
                Traditional methods of assuming a uniform
                temperature and no process variation can lead to
                gross inaccuracies even for system-level design,
                thus it is critical to consider the effects of
                process variation and temperature variation during
                early design exploration. In this paper, we
                describe the implementation of an
                architecture-level early-stage design space
                exploration tool that incorporates the effect of
                process and temperature variation for
                Network-on-chips(NoC). The tool is used to study
                the impact of process and temperature variations
                on power and energy-delay-product-per-flit metrics
                for different NoC architectures, and our
                simulation results show that design choices are
                influenced by the effects of process and
                temperature variation, thus demonstrating the
                importance of considering, and enabling the
                high-level impact analysis of process and
                temperature variation early in the design flow.},
      URL = {http://www.gigascale.org/pubs/1288.html}
  }
  

Posted by Bin Li on 22 Apr 2008..

Notice: This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright.