Search: 
 
Commands
  Search database
  Annual Summary 07-08:
        Full Summary

Quick search by ...
Theme
  alternative
concurrent
core
resilient
heterogeneous
infrastructure
microarch
power
reliable
roadmap
self_test
soft
verification

Design Driver
  driver
ambient
gateway
Year
  2008
2007
2006
2005
2004
2003
2002
2001
2000
1999
1998

Group
  2006faculty
bee2
bk_partitioning
bk_placement
bk_routing
bookshelf
embedded
fabricsthrust
faculty
fresco
gsrc
gsrcadmin
gsrc_faculty
gtx
infrax
marcov
mescal
metropolis
nexsis
polis
ptolemy
semantics
sig_modeling
sig_power
sig_uarch
sig_verification
testthrust
theme_leaders
 System-Level Synthesis - Functions, Architectures, and Communications
Douglas Densmore, Jason Cong, Radu Marculescu, Alberto Sangiovanni-Vincentelli, Clas Jacobson

Citation
Douglas Densmore, Jason Cong, Radu Marculescu, Alberto Sangiovanni-Vincentelli, Clas Jacobson. "System-Level Synthesis - Functions, Architectures, and Communications". Talk or presentation, 21, April, 2008; Full-day Tutorial at Asia & South-Pacific Design Automation Conference (ASP-DAC), Seoul, Korea, Jan. 2008.

Abstract

Each of the grand themes in the future of design of integrated systems and circuits proposes to develop solutions addressing a particular problem, such as power, concurrency, variability or reliability, and brings together aspects from multiple communities such as modeling, architecture exploration, design synthesis, verification, and test. To do this successfully requires an underlying and common design technology framework for complex heterogeneous systems, which can be shared over technology domains and optimization targets. At GSRC, we have expended considerable effort in developing the basic foundations for such a framework. Yet, while we have made major inroads, plenty of challenges remain to be resolved if we want to successfully address the challenges raised by the technology advances. More specifically, the following design needs can be identified:

  • Formal specifications that include declarative and operational components expressed in continuous and discrete time domains.
  • Design as a formally verified refinement process on a set of consistent abstraction layers where appropriate interfaces are built to handle heterogeneous signal domains, thereby ensuring vertical consistency.
  • Optimized and automatic design space exploration with heterogeneous implementation architectures.
  • Mapping of functionality onto architectures exploiting multi-processor optimized compilers, high-level hardware synthesis, and automatic communication synthesis.
  • Automatic extraction of architecture models with stochastic models to capture uncertainties typical of nano-fabrics and mapping of functionalities onto these architectures with optimization of expected performance and cost.
  • An integration framework based on formalized models where the design process can be adaptively defined according to the application domain and offering the opportunity to different constituencies to leverage each other's work.

This tutorial covers recent advances in system-level design and synthesis achieved in the core foundations for heterogeneous system-level design of the Giga-scale System-level Research Center (GSRC). We start with the foundations of the methodology posed as the basis for the multi-year effort of this theme that has been adopted broadly in industry: platform-based design. Following the introduction of the overall methodology, we proceed to present the development of an integration framework, Metropolis II, that builds upon the work of Metropolis. This framework aims at the system design problem where software and hardware are important implementation methods but are determined by overall system consideration and specification. We describe the execution semantics as well as the modeling approach we have followed. This framework and the methodology it supports are exemplified with a few test cases taken from our industrial partners in particular, automobiles and building management. The second part of the tutorial presents recent developments in automatic system level synthesis for complex functional blocks starting from behavior-level specification such as C, C++, SystemC, or Metropolis metamodels. We will present latest results on constraint-driven scheduling from totally untimed models or partially timed models, resource binding and microarchitecture generation for area, performance, and power optimization, and simultaneous behavior and communication synthesis. We shall also present the results on synthesis of application-specific instruction-set processor (ASIPs) as an alternative solution for efficient implementation of the complex function blocks. These techniques have been integrated into the xPilot synthesis system and we shall discuss its results on several real-life examples. The third part of the tutorial addresses the emerging area of NoC design and presents several research issues where the concept of "network" is at the forefront of multi-core processing. Specifically, we plan to discuss performance models and optimization techniques that can be used to design different NoC architectures for multimedia applications, while reasoning about performance, energy, and fault-tolerance tradeoffs. To better understand the advantages in terms of area, performance, and energy consumption offered by the NoC approach, we discuss a concrete NoC-based implementation of an MPEG-2 encoder and provide direct measurements using an FPGA prototype and actual video clips. Finally, we present the practice and results of these state-of-art system-level design and synthesis techniques in an industrial setting. In particular the system level design issues that arise in incorporating networked embedded systems in infrastructure areas (building functionality, HVAC/R, power generation and distribution) are covered through several examples.

Electronic downloads

Citation formats  

  • HTML
    Douglas Densmore, Jason Cong, Radu Marculescu, Alberto
    Sangiovanni-Vincentelli, Clas Jacobson. <a
    href="http://www.gigascale.org/pubs/1286.html"><i>System-Level
    Synthesis - Functions, Architectures, and
    Communications</i></a>, Talk or presentation, 
    21, April, 2008; Full-day Tutorial at Asia &
    South-Pacific Design Automation Conference (ASP-DAC), Seoul,
    Korea, Jan. 2008.
  • Plain text
    Douglas Densmore, Jason Cong, Radu Marculescu, Alberto
    Sangiovanni-Vincentelli, Clas Jacobson. "System-Level
    Synthesis - Functions, Architectures, and Communications".
    Talk or presentation,  21, April, 2008; Full-day Tutorial at
    Asia & South-Pacific Design Automation Conference (ASP-DAC),
    Seoul, Korea, Jan. 2008.
  • BibTeX
    @presentation{DensmoreCongMarculescuSangiovanni-VincentelliJacobson2008,
        author = {Douglas Densmore and Jason Cong and Radu
                  Marculescu and Alberto Sangiovanni-Vincentelli and
                  Clas Jacobson},
        title = {System-Level Synthesis - Functions, Architectures,
                  and Communications},
        day = {21},
        month = {April},
        year = {2008},
        note = {Full-day Tutorial at Asia & South-Pacific Design
                  Automation Conference (ASP-DAC), Seoul, Korea,
                  Jan. 2008.},
        URL = {http://www.gigascale.org/pubs/1286.html}
    }
    

Posted by Douglas Densmore, PhD on 22 Apr 2008..

Notice: This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright.

 
You are not logged in
©1998-2008 GSRC