Citation
Niranjan Soundararajan, Aditya Yanamandra, Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Anand Sivasubramaniam, Mary Jane Irwin. "Analysis and solutions to Issue Queue Process Variation". Dependable Systems and Networks - DCCS, June, 2008.

Abstract
The last few years have witnessed an unprecedented explosion in transistor densities. Diminutive feature sizes have enabled microprocessor designers to break the billion-transistors per chip mark. However various new reliability challenges such as Process Variation (PV) have emerged that can no longer be ignored by chip designers. In this paper, we provide a comprehensive analysis of the effects of PV on the microprocessor’s Issue Queue. Variations can slow down issue queue entries and result in as much as 20.5% performance degradation. To counter this, we look at different solutions that include Instruction Steering, Operand- and Port- switching mechanisms. Given that PV is non-deterministic at design-time, our mechanisms allow the fast and slow issue-queue entries to co-exist in turn enabling instruction dispatch, issue and forwarding to proceed with minimal stalls. Evaluation on a detailed simulation environment indicates that the proposed mechanisms can reduce performance degradation due to PV to a low 1.3%.

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Citation formats

• HTML

  Niranjan Soundararajan, Aditya Yanamandra, Chrysostomos
  Nicopoulos, Vijaykrishnan Narayanan, Anand Sivasubramaniam,
  Mary Jane Irwin. <a
  href="http://www.gigascale.org/pubs/1264.html">Analysis
  and solutions to Issue Queue Process Variation</a>,
  Dependable Systems and Networks - DCCS, June, 2008.

• Plain text

  Niranjan Soundararajan, Aditya Yanamandra, Chrysostomos
  Nicopoulos, Vijaykrishnan Narayanan, Anand Sivasubramaniam,
  Mary Jane Irwin. "Analysis and solutions to Issue Queue
  Process Variation". Dependable Systems and Networks - DCCS,
  June, 2008.

• BibTeX

  @inproceedings{SoundararajanYanamandraNicopoulosNarayananSivasubramaniam08_AnalysisSolutionsToIssueQueueProcessVariation,
      author = {Niranjan Soundararajan and Aditya Yanamandra and
                Chrysostomos Nicopoulos and Vijaykrishnan
                Narayanan and Anand Sivasubramaniam and Mary Jane
                Irwin},
      title = {Analysis and solutions to Issue Queue Process
                Variation},
      booktitle = {Dependable Systems and Networks - DCCS},
      month = {June},
      year = {2008},
      abstract = {The last few years have witnessed an unprecedented
                explosion in transistor densities. Diminutive
                feature sizes have enabled microprocessor
                designers to break the billion-transistors per
                chip mark. However various new reliability
                challenges such as Process Variation (PV) have
                emerged that can no longer be ignored by chip
                designers. In this paper, we provide a
                comprehensive analysis of the effects of PV on the
                microprocessor’s Issue Queue. Variations can slow
                down issue queue entries and result in as much as
                20.5% performance degradation. To counter this, we
                look at different solutions that include
                Instruction Steering, Operand- and Port- switching
                mechanisms. Given that PV is non-deterministic at
                design-time, our mechanisms allow the fast and
                slow issue-queue entries to co-exist in turn
                enabling instruction dispatch, issue and
                forwarding to proceed with minimal stalls.
                Evaluation on a detailed simulation environment
                indicates that the proposed mechanisms can reduce
                performance degradation due to PV to a low 1.3%.},
      URL = {http://www.gigascale.org/pubs/1264.html}
  }
  

Posted by Niranjan Soundararajan on 2 Apr 2008..

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