Citation
Ramakrishnan Krishnan, Rajaraman Ramanarayanan, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Kenan Unlu. "Hierarchical Soft Error Estimation Tool (HSEET)". International Symposium on Quality Electronic Design (ISQED), March, 2008.

Abstract
Radiation induced soft errors have become an important reliability concern in the sub-nanometer regime. Therefore, it is imperative to devise methods to predict the Soft Error Rates (SER) quickly and accurately in combinational circuits. In this paper, we present a novel technique and a tool to compute the SERs of designs employing hierarchical architectures such as adders and multipliers. The technique uses pre-characterized blocks for current generation and propagation and probability theory to estimate the SER in hierarchical architectures. The analysis results of different hierarchical architectures, based on characterization of basic blocks such as muxes, counters and partial product generators using the new technique, are presented in this paper. The run time for most of the designs were in the order of few minutes and we obtain an average speedup of 14084X times over HSPICE and 12.25X times over a contemporary tool SEAT-LA. We have also demonstrated the scalability of our technique for various hierarchical circuits. Our technique can also be extended to any block based architecture.

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Citation formats

• HTML

  Ramakrishnan Krishnan, Rajaraman Ramanarayanan,
  Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Kenan
  Unlu. <a
  href="http://www.gigascale.org/pubs/1251.html">Hierarchical
  Soft Error Estimation Tool (HSEET)</a>, International
  Symposium on Quality Electronic Design (ISQED), March, 2008.

• Plain text

  Ramakrishnan Krishnan, Rajaraman Ramanarayanan,
  Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Kenan
  Unlu. "Hierarchical Soft Error Estimation Tool (HSEET)".
  International Symposium on Quality Electronic Design
  (ISQED), March, 2008.

• BibTeX

  @inproceedings{KrishnanRamanarayananNarayananXieIrwinUnlu08_HierarchicalSoftErrorEstimationToolHSEET,
      author = {Ramakrishnan Krishnan and Rajaraman Ramanarayanan
                and Vijaykrishnan Narayanan and Yuan Xie and Mary
                Jane Irwin and Kenan Unlu},
      title = {Hierarchical Soft Error Estimation Tool (HSEET)},
      booktitle = {International Symposium on Quality Electronic
                Design (ISQED)},
      month = {March},
      year = {2008},
      abstract = {Radiation induced soft errors have become an
                important reliability concern in the sub-nanometer
                regime. Therefore, it is imperative to devise
                methods to predict the Soft Error Rates (SER)
                quickly and accurately in combinational circuits.
                In this paper, we present a novel technique and a
                tool to compute the SERs of designs employing
                hierarchical architectures such as adders and
                multipliers. The technique uses pre-characterized
                blocks for current generation and propagation and
                probability theory to estimate the SER in
                hierarchical architectures. The analysis results
                of different hierarchical architectures, based on
                characterization of basic blocks such as muxes,
                counters and partial product generators using the
                new technique, are presented in this paper. The
                run time for most of the designs were in the order
                of few minutes and we obtain an average speedup of
                14084X times over HSPICE and 12.25X times over a
                contemporary tool SEAT-LA. We have also
                demonstrated the scalability of our technique for
                various hierarchical circuits. Our technique can
                also be extended to any block based architecture.},
      URL = {http://www.gigascale.org/pubs/1251.html}
  }
  

Posted by Ramakrishnan Krishnan on 26 Mar 2008..

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