Citation
Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K Mishra, Vijaykrishnan Narayanan, Yuan Xie, Chita R Das. "MIRA: A Multi-Layered On-Chip Interconnect Router Architecture". International Symposium on Computer Architecture, Pennsylvania State University, June, 2008.

Abstract
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP/multi-core/SoC systems in deep sub-micron technology. However, almost all prior studies have focused on 2D NoC designs. Since three dimensional (3D) integration has emerged to mitigate the interconnect delay problem, exploring the NoC design space in 3D can provide ample opportunities to design high performance and energy-efficient NoC architectures. In this paper, we propose a 3D stacked NoC router architecture, called MIRA, which unlike the 3D routers in previous works, is stacked into multiple layers and optimized to reduce the overall area requirements and power consumption. We discuss the design details of a four-layer 3D NoC and its enhanced version with additional express channels, and compare them against a (6×6) 2D design and a baseline 3D design. All the designs are evaluated using a cycle-accurate 3D NoC simulator, and integrated with the Orion power model for performance and power analysis. The simulation results with synthetic and application traces demonstrate that the proposed multi-layered NoC routers can outperform the 2D and naïve 3D designs in terms of performance and power. It can achieve up to 42% reduction in power consumption and up to 51% improvement in average latency with synthetic workloads. With real workloads, these benefits are around 67% and 38%, respectively.

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Citation formats

• HTML

  Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K
  Mishra, Vijaykrishnan Narayanan, Yuan Xie, Chita R Das.
  <a
  href="http://www.gigascale.org/pubs/1236.html">MIRA:
  A Multi-Layered On-Chip Interconnect Router
  Architecture</a>, International Symposium on Computer
  Architecture, Pennsylvania State University, June, 2008.

• Plain text

  Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K
  Mishra, Vijaykrishnan Narayanan, Yuan Xie, Chita R Das.
  "MIRA: A Multi-Layered On-Chip Interconnect Router
  Architecture". International Symposium on Computer
  Architecture, Pennsylvania State University, June, 2008.

• BibTeX

  @inproceedings{ParkEachempatiDasMishraNarayananXieDas08_MIRAMultiLayeredOnChipInterconnectRouterArchitecture,
      author = {Dongkook Park and Soumya Eachempati and Reetuparna
                Das and Asit K Mishra and Vijaykrishnan Narayanan
                and Yuan Xie and Chita R Das},
      title = {MIRA: A Multi-Layered On-Chip Interconnect Router
                Architecture},
      booktitle = {International Symposium on Computer Architecture},
      organization = {Pennsylvania State University},
      month = {June},
      year = {2008},
      abstract = {Recently, Network-on-Chip (NoC) architectures have
                gained popularity to address the interconnect
                delay problem for designing CMP/multi-core/SoC
                systems in deep sub-micron technology. However,
                almost all prior studies have focused on 2D NoC
                designs. Since three dimensional (3D) integration
                has emerged to mitigate the interconnect delay
                problem, exploring the NoC design space in 3D can
                provide ample opportunities to design high
                performance and energy-efficient NoC
                architectures. In this paper, we propose a 3D
                stacked NoC router architecture, called MIRA,
                which unlike the 3D routers in previous works, is
                stacked into multiple layers and optimized to
                reduce the overall area requirements and power
                consumption. We discuss the design details of a
                four-layer 3D NoC and its enhanced version with
                additional express channels, and compare them
                against a (6×6) 2D design and a baseline 3D
                design. All the designs are evaluated using a
                cycle-accurate 3D NoC simulator, and integrated
                with the Orion power model for performance and
                power analysis. The simulation results with
                synthetic and application traces demonstrate that
                the proposed multi-layered NoC routers can
                outperform the 2D and naïve 3D designs in terms of
                performance and power. It can achieve up to 42%
                reduction in power consumption and up to 51%
                improvement in average latency with synthetic
                workloads. With real workloads, these benefits are
                around 67% and 38%, respectively.},
      URL = {http://www.gigascale.org/pubs/1236.html}
  }
  

Posted by Aditya Yanamandra on 25 Mar 2008..

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