Citation
jung-hwan choi, jayathi murthy, Kaushik Roy. "The Effect of Process Variation on Device Temperature in FinFET Circuits". ICCAD, November, 2007.

Abstract
With technology scaling, devices are increasingly prone to process variations. These variations cause a large spread in leakage power, since it is extremely sensitive to process variations, which in turn results in larger temperature variations across different dies. In this paper, we investigate the temperature variations in FinFET circuits considering variations in following parameters (i) channel length and (ii) body thickness. We estimate temperature variation under process fluctuation by Monte Carlo simulation with thermal models to solve temperature and leakage power self-consistently. The results show that high activity circuits exhibit larger temperature variations since increased temperature increments leakage power and vice versa. It is also shown that under moderate process variation (3σ=10% for channel length and body thickness) and a nominal primary input activity of 0.4, thermal runaway can occur in more than 15% of chips in 28nm FinFET technology, severely degrading manufacturing yield.

Electronic downloads

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Citation formats

• HTML

  jung-hwan choi, jayathi murthy, Kaushik Roy. <a
  href="http://www.gigascale.org/pubs/1191.html">The
  Effect of Process Variation on Device Temperature in FinFET
  Circuits</a>, ICCAD, November, 2007.

• Plain text

  jung-hwan choi, jayathi murthy, Kaushik Roy. "The Effect of
  Process Variation on Device Temperature in FinFET Circuits".
  ICCAD, November, 2007.

• BibTeX

  @inproceedings{choimurthyRoy2007,
      author = {jung-hwan choi and jayathi murthy and Kaushik Roy},
      title = {The Effect of Process Variation on Device
                Temperature in FinFET Circuits},
      booktitle = {ICCAD},
      month = {November},
      year = {2007},
      URL = {http://www.gigascale.org/pubs/1191.html}
  }
  

Posted by Swaroop Ghosh on 24 Jan 2008..

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