Citation
Girish V. Varatkar, Naresh Shanbhag. "Variation-Tolerant Motion Estimation Architecture". IEEE Workshop on Signal Processing Systems, October, 2007.

Abstract
In this paper, we study the trade-off between energy-efficiency and variation-tolerance of an error-resilient motion estimation architecture. Error-resiliency is incorporated via algorithmic noise-tolerance (ANT) where an input subsampled replica (ISR) of the main sum-of-absolute-difference (MSAD) block is employed for detecting and correcting errors in the MSAD block. This architecture is referred to as ISR-ANT. In the presence of process variations, the average peak signal-to-noise ratio(PSNR) of ISR-ANT architecture increases by up to 1.8dB over that of the conventional architecture in 130nm IBM process technology. Furthermore, the $PSNR$ variation is also reduced by 7x over that of the conventional architecture at the slow corner while achieving a power reduction of 33%.

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• HTML

  Girish V. Varatkar, Naresh Shanbhag. <a
  href="http://www.gigascale.org/pubs/1166.html">Variation-Tolerant
  Motion Estimation Architecture</a>, IEEE Workshop on
  Signal Processing Systems, October, 2007.

• Plain text

  Girish V. Varatkar, Naresh Shanbhag. "Variation-Tolerant
  Motion Estimation Architecture". IEEE Workshop on Signal
  Processing Systems, October, 2007.

• BibTeX

  @inproceedings{VaratkarShanbhag2007,
      author = {Girish V. Varatkar and Naresh Shanbhag},
      title = {Variation-Tolerant Motion Estimation Architecture},
      booktitle = {IEEE Workshop on Signal Processing Systems},
      month = {October},
      year = {2007},
      URL = {http://www.gigascale.org/pubs/1166.html}
  }
  

Posted by Girish V. Varatkar on 11 Jan 2008..

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