Citation
Girish V. Varatkar, Sriram Narayanan, Naresh Shanbhag, Douglas L. Jones. "Sensor Network-On-Chip". International Symposium on SOC, November, 2007.

Abstract
In this paper, we present the sensor network-on-a-chip (SNOC) paradigm for designing robust and energy-efficient systems-on-a-chip (SOC). In this paradigm, computation in the presence of nanometer non-idealities such as process variations, leakage and noise is viewed as an estimation problem. Robust statistical signal processing theory is then employed to recover the performance of the system in the presence of errors especially timing errors. We apply this framework to design an energy-efficient and robust PN-code acquisition system for the wireless CDMA2000 standard. Simulations in IBM's 130nm CMOS process technology demonstrate up to 36% power savings compared to the conventional architecture for a detection probability of P_D=0.5.

Electronic downloads

• socv5.pdf · application/pdf · 237 kbytes

Citation formats

• HTML

  Girish V. Varatkar, Sriram Narayanan, Naresh Shanbhag,
  Douglas L. Jones. <a
  href="http://www.gigascale.org/pubs/1164.html">Sensor
  Network-On-Chip</a>, International Symposium on SOC,
  November, 2007.

• Plain text

  Girish V. Varatkar, Sriram Narayanan, Naresh Shanbhag,
  Douglas L. Jones. "Sensor Network-On-Chip". International
  Symposium on SOC, November, 2007.

• BibTeX

  @inproceedings{VaratkarNarayananShanbhagJones2007,
      author = {Girish V. Varatkar and Sriram Narayanan and Naresh
                Shanbhag and Douglas L. Jones},
      title = {Sensor Network-On-Chip},
      booktitle = {International Symposium on SOC},
      month = {November},
      year = {2007},
      URL = {http://www.gigascale.org/pubs/1164.html}
  }
  

Posted by Girish V. Varatkar on 11 Jan 2008..

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