Citation
A. Krstic, J.-J. Liou, Y.-M. Jiang, K.-T. Cheng. "Delay Testing Considering Crosstalk-Induced Effects". Proceedings of International Test Conference, October, 2001.

Abstract
The increased noise/interference effects, such as crosstalk, power supply noise,substrate noise and distributed delay variations lead to increased signal integrity problems in deep submicron designs. These problems can cause logic errors and/or performance degradation and need to be addressed both in the design for deep submicron and testing for deep submicron phase. Existing delay testing techniques cannot capture the effects of noise on the cell/interconnect delays. In this paper, we address the problem of delay testing considering crosstalk-induced delay effects. We propose solutions for target fault selection and pattern generation. The key elements of our strategy are performance sensitivity analysis with respect to crosstalk noise and a Genetic Algorithm (GA) based vector generation technique. The role of performance sensitivity analysis is to consider the effects of crosstalk noise during the target fault selection process. Next, for each selected fault consisting of a path and a set of crosstalk noise sources interacting with the path, we apply our iterative GA-based pattern generation process. Our goal is to derive a test that produces large crosstalk-induced delay effect on the given path. Our technique allows considering any number of coupling sources along the target path. Due to its flexibility, efficiency and scalability, the technique can be applied to large circuits.

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Citation formats

• HTML

  A. Krstic, J.-J. Liou, Y.-M. Jiang, K.-T. Cheng. <a
  href="http://www.gigascale.org/pubs/106.html">Delay
  Testing Considering Crosstalk-Induced Effects</a>,
  Proceedings of International Test Conference, October, 2001.

• Plain text

  A. Krstic, J.-J. Liou, Y.-M. Jiang, K.-T. Cheng. "Delay
  Testing Considering Crosstalk-Induced Effects". Proceedings
  of International Test Conference, October, 2001.

• BibTeX

  @inproceedings{KrsticLiouJiangCheng01_DelayTestingConsideringCrosstalkInducedEffects,
      author = {A. Krstic and J.-J. Liou and Y.-M. Jiang and K.-T.
                Cheng},
      title = {Delay Testing Considering Crosstalk-Induced Effects},
      booktitle = {Proceedings of International Test Conference},
      month = {October},
      year = {2001},
      abstract = {The increased noise/interference effects, such as
                crosstalk, power supply noise,substrate noise and
                distributed delay variations lead to increased
                signal integrity problems in deep submicron
                designs. These problems can cause logic errors
                and/or performance degradation and need to be
                addressed both in the design for deep submicron
                and testing for deep submicron phase. Existing
                delay testing techniques cannot capture the
                effects of noise on the cell/interconnect delays.
                In this paper, we address the problem of delay
                testing considering crosstalk-induced delay
                effects. We propose solutions for target fault
                selection and pattern generation. The key elements
                of our strategy are performance sensitivity
                analysis with respect to crosstalk noise and a
                Genetic Algorithm (GA) based vector generation
                technique. The role of performance sensitivity
                analysis is to consider the effects of crosstalk
                noise during the target fault selection process.
                Next, for each selected fault consisting of a path
                and a set of crosstalk noise sources interacting
                with the path, we apply our iterative GA-based
                pattern generation process. Our goal is to derive
                a test that produces large crosstalk-induced delay
                effect on the given path. Our technique allows
                considering any number of coupling sources along
                the target path. Due to its flexibility,
                efficiency and scalability, the technique can be
                applied to large circuits. },
      URL = {http://www.gigascale.org/pubs/106.html}
  }
  

Posted by Angela Krstic, PhD on 17 Aug 2001..

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