Citation
Umit Y. Ogras, Radu Marculescu. "Analytical Router Modeling for Networks-on-Chip Performance Analysis". Design, Automation and Test in Europe Conference, April, 2007.

Abstract
Networks-on-Chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters affect the actual network performance. Therefore, it is practically impossible to use simulation for optimization purposes. In this paper, we first present a generalized router model and then utilize this novel model for doing NoC performance analysis. The proposed model can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop. The accuracy of our approach and its practical use is illustrated through extensive simulation results.

Electronic downloads

• http://www.ece.cmu.edu/~sld/pubs/papers/07f_3_768.pdf

Citation formats

• HTML

  Umit Y. Ogras, Radu Marculescu. <a
  href="http://www.gigascale.org/pubs/1013.html">Analytical
  Router Modeling for Networks-on-Chip Performance
  Analysis</a>, Design, Automation and Test in Europe
  Conference, April, 2007.

• Plain text

  Umit Y. Ogras, Radu Marculescu. "Analytical Router Modeling
  for Networks-on-Chip Performance Analysis". Design,
  Automation and Test in Europe Conference, April, 2007.

• BibTeX

  @inproceedings{OgrasMarculescu07_AnalyticalRouterModelingForNetworksonChipPerformance,
      author = {Umit Y. Ogras and Radu Marculescu},
      title = {Analytical Router Modeling for Networks-on-Chip
                Performance Analysis},
      booktitle = {Design, Automation and Test in Europe Conference},
      month = {April},
      year = {2007},
      abstract = {Networks-on-Chip (NoCs) have recently emerged as a
                scalable alternative to classical bus and
                point-to-point architectures. To date, performance
                evaluation of NoC designs is largely based on
                simulation which, besides being extremely slow,
                provides little insight on how different design
                parameters affect the actual network performance.
                Therefore, it is practically impossible to use
                simulation for optimization purposes. In this
                paper, we first present a generalized router model
                and then utilize this novel model for doing NoC
                performance analysis. The proposed model can be
                used not only to obtain fast and accurate
                performance estimates, but also to guide the NoC
                design process within an optimization loop. The
                accuracy of our approach and its practical use is
                illustrated through extensive simulation results.},
      URL = {http://www.gigascale.org/pubs/1013.html}
  }
  

Posted by Umit Y. Ogras on 31 May 2007..

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