Core Design Technology for Complex Heterogeneous Systems
Welcome to the GSRC Website
Adaptive R/F Front End for Wireless Communication
Automated Generation of Application-Aware Error Detectors
Design Space Exploration for a Motion-JPEG Encoder in the Metropolis Design Environment
Error-Tolerant SRAM Design for Ultra-Low Power Standby
Home Gateway
Hybrid Processor Accellerator Coexecution Environment - Where Does the Compiler Come In?
Illinois Reliability and Security Architecture
MetroSPICE++
NOC Performance Optimization via Long-Range Link Insertion
REVEAL - A Scalable Verification Tool for High-Level Verilog Models
Self-Repairing SRAM
Streaming Media over an Application Specific Multiprocessor
Symbolic Reliability Analysis, Vertically-Consistent Spatial Embedding, Tools for Parametric Yield Optimization
UCLA xPilot: a Platform-Based Behavioral Synthesis System
VCEGAR: Verilog CounterExample Guided Abstraction and Refinement
Introduction to GSRC, 2005, Richard Newton