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Bin Li


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   Joint Resource Management for QoS in Many-Core Chips     [ edit ]   
Pub ID:  2012 Authors:  Bin Li, Li‑Shiuan Peh, Li Zhao, Ravi Iyer

With the continuing scaling of semiconductor technologies, many core systems have become the de facto design for modern high performance computer architectures. It is expected that more and more applications with diverse requirements will run simultaneously on the many core platform. However, this will exert contention on shared resources such as the last level cache, network-on-chip bandwidth and off-chip memory bandwidth, thus affecting the performance and quality of service (QoS) significantly. In this environment, efficient resource sharing and a guarantee of a certain level of performance is highly desirable.

Researchers have proposed different techniques to support QoS, but most existing works focus on only one individual resource. Besides, most of these frameworks allocate shared resources statically at the beginning of application runtime, and do not dynamically track, manage and share shared resources across applications. Joint QoS support and coordinated management of those shared resources remains an open problem. It our work, we address this limitation by proposing architectures for joint resource management for QoS support. We then propose dynamic QoS management policies that monitor the resource usage of applications at runtime, then steals resources from the high priority applications for lower priority ones. The goal is to maintain the targeted level of performance for high priority applications while improving the performance of lower priority applications. To the best of our knowledge, this is the first work that considers all the three critical shared resources (cache, NoC and memory) simultaneously for joint QoS support and management. Our evaluation results show that our dynamic resource management policy can improve performance for lower priority applications significantly while maintaining the performance for high priority application, thus demonstrating the effectiveness of our dynamic QoS resource management policy.

Sep 3, 2009,   GSRC Annual Symposium 2009

   ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration
Pub ID:  1389 Authors:  Kambiz Samadi, Andrew Kahng, Bin Li, Li‑Shiuan Peh
As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power has become crucially important. ORION [2] was amongst the first NoC power models released, and has since been fairly widely used for early-stage power estimation of NoCs. However, when validated against recent NoC prototypes - the Intel 80-core Teraflops chip and the Intel Scalable Communications Core (SCC) chip - we saw significant deviation that can lead to erroneous NoC design choices. This prompted our development of ORION 2.0, an extensive enhancement of the original ORION models which includes completely new subcomponent power models, area models, as well as improved and updated technology models. Validating against the two Intel chips saw ORION 2.0 bringing a substantial improvement in accuracy over the original ORION. A case study with these power models plugged within the COSI-OCC NoC design space exploration tool [11] confirms the need for, and value of, accurate early-stage NoC power estimation. To ensure the longevity of ORION 2.0, we will be releasing it wrapped within a semi-automated flow that automatically updates its models as new technology files become available.
Sep 29, 2008,   GSRC Annual Symposium 2008

   Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Pub ID:  113 Authors:  Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li, Li‑Shiuan Peh
Sep 28, 2006,   GSRC Annual Symposium 2006