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authored by
Wen-mei Hwu
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May 10, 2002 -- GSRC Website
Hybrid Processor Accellerator Coexecution Environment - Where Does the Compiler Come In?
Pub ID: 11
Author:
Daniel Burke
Presenter:
Sain‑Zee Ueng
As chip area and transistor count increases, parallel platforms such as multicore architectures and processors with accelerator technology offer a more effective use of real estate and power budget. Unfortunately, there are still many questions to be answered for such approaches. We present what we have identified as the major hurdles and opportunities for these approaches, with great emphasis on compiler technology for parallelism. We discuss our proposed software framework where all accelerators appear to be dynamically linked library functions to the applications software. We also present results of using FPGA technology as accelerators for three example applications.
Mar 14, 2006, GSRC Workshop, March 2006
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