Design Principles for Perturbation Based Computing
Efficient Coding Techniques for Defect Tolerance in Future Nano-Circuits
Error Resilient Low-Power Viterbi Decoders
Implementing Carbon Nanotube Transistors in SPICE++ Prototyping Environment
MCSim: An ASPN Simulator
Misaligned-Carbon-Nanotube-Immune Logic Structures and Metallic-Carbon-Nanotube-Tolerant Circuits
Novel Circuit Fabrics for Networked Computation
Numerical Simulation of Coupled Oscillator Networks
Optimizing System Performance by Leveraging Local Intra-Core Information
Pattern-Based Behavior Synthesis
Run-time Resource Management for NoCs with Multiple Voltage Levels
Sensor Networks-On-Chip
Stochastic Communication: Modeling, Analysis and Optimization
TLM Generation and Verification
Architecture Implications of 3D Integration and Other Technologies
A Biologist's Need for Computation -- Agony & Ecstasy
Alternative Computational Models
Oscillator Networks, their Properties and Potential Applications
Networked Computation
Exploring Unreliable Technology Scaling for High Performance Systems
Coding for High-Defect Fabrics
Imperfection-Immune CNFET Circuits
Stochastic Communication
Concurrent Systems Theme
A Map Reduce Framework for Programming GPUs
Architectural Support to Eliminate Barriers in Parallel Programming and Automatic Parallelization
Reliability-Aware Design for Multi-Processor Systems on Chip
The Core Theme
TLM Functional Verification and Interface to Metro-II
Pattern Identification and Extraction in Behavioral Synthesis and ASIP Designs
Latency-Insensitive Design and Communication-Synthesis
Communication Modeling for System Level Design
Stochastic Design and Analysis of Networks-on-Chip
Rethinking Resilience
Sustaining Error Resiliency: The IBM POWER6TM Microprocessor
Virtualization & Machine Learning: A New Approach to Server HA
CRISTA: An Integrated Technique for Voltage-overscaling and Error Resiliency
A Formal Framework for Validating Application-aware Error Detectors
GSRC Design Drivers
Performance, Energy, and Fault-tolerance Issues in NoC Design Slides in PDF
Collaborative Radio Project Update
Imperfection-Immune Carbon Nanotube FET Circuits
Perturbation Based Computing
Stochastic Sensor Network-on-a-Chip
Using Defect-Map Knowledge for More Efficient Coding
Core Theme Overview and Design Flow
Energy-Aware Design for 1000 Cores: Exploiting VFIs for NoC-Based Systems
MC-Sim: an Efficient Simulation Tool for Heterogeneous Multi-core Systems
MetroSPICE++ Core Update
Synthesis of Reconfigurable High High-Performance Multicore Systems
System-Level Modeling II (Routers)
TLM Verification Tool and Interface to Metro-II
Modeling and Metrics Initiative: In Search of Common Ground
Resilient System Design Theme: Surviving In the Silicon Jungle
The Importance of Test
Exploiting the Synergy Between Fault Tolerance, Manufacturing Test and Debug
CrashTest: Resiliency Analysis Framework
Metrics for Architecture-Level Lifetime Reliability Analysis
Models and Metrics for Test
SymPLFIED: Symbolic Program Level Fault Injection and Error Detection Framework
Reliability Modeling and Simulation for Nanoscale Design
NBTI Induced Performance Degradation in Logic and Memory Circuits: How Effectively Can We Approach a Reliability Solution?
Specification Based Testing vs. Fault Based Testing: Dilemma for Low Cost Testing of Mixed- Signal and RF Circuits
Workloads of the Future
Future Workloads for Designing Future Computers
Print Workload
NERSC Workload Analysis
Where are Internet workloads going?
Workloads of the Future: "Mobility, Community, Serendipity"
Connecting the Unconnected: the networking challenge
Remarks on Workloads of the Future
NVIDIA GPU Computing
GSRC Workshop: Workloads of the Future
High Performance Buildings (Systems) (...and Power...) Challenges for Embedded Systems & Enabling Opprotunities for GSRC
New Automotive DNA
Theoretical Foundations (Alternatives subtheme)
Communication Fabrics
Verification Driven Formal Architecture and Microarchitecture (Requires Windows and IE 6) Slides in PDF
A 4.6Tbits/s 3.6GHz Single-cycle NoC Router with a Novel Switch Allocator in 65nm CMOS
Adaptive Precision Arithmetic (APA) for Error Tolerant Applications
Algorithms for Atomicity
Alternative Computational Models Slides in PDF
An efficient Method to Identify Critical Gates under Circuit Aging
An Emulation Platform for Evaluating Thermal and Reliability Effects in CMPs
An Energy-Efficient Communication Fabric for SNOCs
An Extensible Synthesis Approach for Meeting Latency Requirements in Distributed Systems Slides in PDF
Analysis on Timing Margining Test for High-Speed Serial Interfaces
Application studies on GPU
Application-Aware Error Detectors and their Hardware Implementation Slides in PDF
Automatable Hazard Checking for Transaction Level Microarchitecture Models
Automated Design of Misalignment-Immune CNT Circuits Slides in PDF
BulletProof Microprocessor Pipelines
Carbon Nanotube FET circuits: Scalability and Design Techniques for Living with Imperfections
Cm-Range Wireless Communication
Communication Modeling for System-Level Design
Concurrent Systems Theme Slides in PDF
Cooperative Hardware-Software Reliability
COSI: The Communication Synthesis Infrastructure
CRISTA: A Process-Tolerant, Low Voltage Design Methodology using Adaptive Clocking for High-Performance Processors
Dense Network for Storage
Design Paradigm for Low-Power, Variation-Resilient Systems using Adaptive Quality Modulation
Digitally-Assisted Analog Testing
Efficient Coding techniques for Defect Tolerance in Future Nano-circuits
Efficient Parallelization of H.264 Decoding with Macro Block Level Scheduling
Error Resilient System Architecture (ERSA) for Probabilistic Applications
Evaluating the Role of Scratchpad Memories in Multi-core for Sparse Matrix Computations
FRiCLe: Field Reparable Control Logic
From Quark to Jaguar: Network-on-Chips as Quantum Systems
Graphical Model Inference using GPUs
GSRC Design Drivers Slides in PDF
Highlights of Core Theme
Highlights of Core Theme Slides in PDF
Inferno: Verification With Transactions
Low Energy Logic using Current Mode Pass Transistor Logic
Low-Cost Test of OFDM Transmitter Specifications for QoS (EVM/BER)
Modeling a Heterogeneous Multiprocessor for Software Defined Radio: Performance Backwards Annotation
Multiprocessor Approach to Error Prevention in Applications
NBTI under Arbitrary Dynamic Temperature Variation
NoC Overlaid with Multi-Band RF-Interconnect
Optimization for Highly Parallel Systems Slides in PDF
Platform-Based Design of a Low Power MB-OFDM UWB Receiver Front-end
Post Fabrication Adaptation to Process Variations and Manufacturing Defects
Prediction-based Flow Control for Networks-on-Chip
PriM: Verification Driven Formal Architecture and Microarchitecture Modeling
Probabilistic Compensation in Digital Filters Using Linearized Checksums
Profile-Driven Energy Reduction in Network-on-Chips
RAMP Blue
RAMP Blue: A Message-Passing Many-Core System in FPGAs Slides in PDF
Research Accelerator for Multiple Processors - RDL Overview & Timing
Resilient System Design Theme: Surviving In the Silicon Jungle Slides in PDF
Revisiting the Sequential Programming Model for Multi-Core
Runtime Validation of Memory Ordering Using Constraint Graph Checking
Self-Healing Emulation on BEE2 System
Smart Control Independence for Implicit Parallelization
StageNet: An Adaptive CMP System for Wearout Tolerant Computing
State of the Center Slides in PDF
Statistical Sensor Network-On-Chip
Stochastic Analysis of Controller Area Network Message Latencies
Stochastic Communication: Modeling, Analysis, Optimization
Synthesis for Distributed Automotive Systems
System Level Modeling of Wireless Communication Link for Intelligent Tires
Temperature Compensated Oscillator
Test Strategy and Yield Analysis for Multi-core systems with Spares
Uncovering Implicit Loop Level Parallelism in C/C++ Applications
Verification of Transactional Memory Implementations and Programs
Verification-Guided Error Resilience
VIZOR: Virtually Zero Margin Adaptive RF for Ultra Low Power Wireless Communication
Voltage-Frequency Island (VFI) Partitioning for GALS-based NoCs
An Extensible Synthesis Approach for Meeting Latency Requirements in Distributed Systems
Application-Aware Error Detectors and their Hardware Implementation
Automated Design of Misalignment-Immune CNT Circuits
RAMP Blue: A Message-Passing Many-Core System in FPGAs
Proposals for Metro II Execution Semantics for Mapping
Analysis and Implementation of Sensors for System-Level Reliability Monitoring
Implicitly Parallel Flow -- Thrust Highlights
TLM Generation and Verification and Interface to Metro-II
Concurrent Systems Theme: Natural Programming Models Group
Hybrid System Simulation and Abstraction: MetroSPICE++
Yield-Centric Design Framework for Low Voltage Robust Systems
COSI
StageNet: A Wearout Tolerant CMP System
