Design Principles for Perturbation Based Computing
Efficient Coding Techniques for Defect Tolerance in Future Nano-Circuits
Error Resilient Low-Power Viterbi Decoders
Implementing Carbon Nanotube Transistors in SPICE++ Prototyping Environment
MCSim: An ASPN Simulator
Misaligned-Carbon-Nanotube-Immune Logic Structures and Metallic-Carbon-Nanotube-Tolerant Circuits
Novel Circuit Fabrics for Networked Computation
Numerical Simulation of Coupled Oscillator Networks
Optimizing System Performance by Leveraging Local Intra-Core Information
Pattern-Based Behavior Synthesis
Run-time Resource Management for NoCs with Multiple Voltage Levels
Sensor Networks-On-Chip
Stochastic Communication: Modeling, Analysis and Optimization
TLM Generation and Verification
A 4.6Tbits/s 3.6GHz Single-cycle NoC Router with a Novel Switch Allocator in 65nm CMOS
Adaptive Precision Arithmetic (APA) for Error Tolerant Applications
Algorithms for Atomicity
An efficient Method to Identify Critical Gates under Circuit Aging
An Emulation Platform for Evaluating Thermal and Reliability Effects in CMPs
An Energy-Efficient Communication Fabric for SNOCs
Analysis on Timing Margining Test for High-Speed Serial Interfaces
Application studies on GPU
Automatable Hazard Checking for Transaction Level Microarchitecture Models
BulletProof Microprocessor Pipelines
Carbon Nanotube FET circuits: Scalability and Design Techniques for Living with Imperfections
Cm-Range Wireless Communication
Communication Modeling for System-Level Design
Cooperative Hardware-Software Reliability
COSI: The Communication Synthesis Infrastructure
CRISTA: A Process-Tolerant, Low Voltage Design Methodology using Adaptive Clocking for High-Performance Processors
Dense Network for Storage
Design Paradigm for Low-Power, Variation-Resilient Systems using Adaptive Quality Modulation
Digitally-Assisted Analog Testing
Efficient Coding techniques for Defect Tolerance in Future Nano-circuits
Efficient Parallelization of H.264 Decoding with Macro Block Level Scheduling
Error Resilient System Architecture (ERSA) for Probabilistic Applications
Evaluating the Role of Scratchpad Memories in Multi-core for Sparse Matrix Computations
FRiCLe: Field Reparable Control Logic
From Quark to Jaguar: Network-on-Chips as Quantum Systems
Graphical Model Inference using GPUs
Inferno: Verification With Transactions
Low Energy Logic using Current Mode Pass Transistor Logic
Low-Cost Test of OFDM Transmitter Specifications for QoS (EVM/BER)
Modeling a Heterogeneous Multiprocessor for Software Defined Radio: Performance Backwards Annotation
Multiprocessor Approach to Error Prevention in Applications
NBTI under Arbitrary Dynamic Temperature Variation
NoC Overlaid with Multi-Band RF-Interconnect
Platform-Based Design of a Low Power MB-OFDM UWB Receiver Front-end
Post Fabrication Adaptation to Process Variations and Manufacturing Defects
Prediction-based Flow Control for Networks-on-Chip
PriM: Verification Driven Formal Architecture and Microarchitecture Modeling
Probabilistic Compensation in Digital Filters Using Linearized Checksums
Profile-Driven Energy Reduction in Network-on-Chips
RAMP Blue
Research Accelerator for Multiple Processors - RDL Overview & Timing
Revisiting the Sequential Programming Model for Multi-Core
Runtime Validation of Memory Ordering Using Constraint Graph Checking
Self-Healing Emulation on BEE2 System
Smart Control Independence for Implicit Parallelization
StageNet: An Adaptive CMP System for Wearout Tolerant Computing
Statistical Sensor Network-On-Chip
Stochastic Analysis of Controller Area Network Message Latencies
Stochastic Communication: Modeling, Analysis, Optimization
Synthesis for Distributed Automotive Systems
System Level Modeling of Wireless Communication Link for Intelligent Tires
Temperature Compensated Oscillator
Test Strategy and Yield Analysis for Multi-core systems with Spares
Uncovering Implicit Loop Level Parallelism in C/C++ Applications
Verification of Transactional Memory Implementations and Programs
Verification-Guided Error Resilience
VIZOR: Virtually Zero Margin Adaptive RF for Ultra Low Power Wireless Communication
Voltage-Frequency Island (VFI) Partitioning for GALS-based NoCs
A Constraint Network A Constraint Network Based Solution to Code Parallelization
A Decomposition-based Constraint Optimization Approach for Statically Scheduling Task Graphs to Multiprocessors
A Framework for Reliability Analysis Considering Both System Fault Tolerance and Component Test Quality
A New Paradigm for Low-power and Robust Circuit Synthesis Under Process Variations Using Critical Path Isolation
Application-aware Robust Computing Framework
Architectural Exploration Architectural Exploration in NoC Design
Architecture & Microarchitecture Models for Design Validation
Automated Derivation of Application-Aware Error Detectors using Static Analysis
Behavior and Communication Co-Optimization for Systems with Sequential Communication Media
BER Estimation for High-Speed Serial Links
BulletProof: Architecting Reliable Systems
Energy-efficient Motion Estimation Using Error-tolerance
Evaluating Reliability of On-Chip SRAM Arrays using Dynamic Stability Analysis
Expanding the IMPACT Toolbox
FLAW:FPGA Lifetime Awareness
Fundamental Redundancy Versus Power Tradeoff in Standby SRAM
High-Level Power Analysis for Multi-Core Chips
Implementation and Demonstartion of Illinois Reliability and Security Engine
Integrating Aging Effects into VLSI Circuit Modeling, Diagnosis and Optimization
Intra-Gate Channel Length Biasing for Transistor-Level Circuit Optimization
ITS: Intelligent Tire System
Low Complexity Video Transcoding with Access Control
MetroSPICE++: Hybrid Simulation using Metropolis and SPICE++
Model-Based Design of Heterogeneous Systems for Fault Tree Analysis
Platform-based Design of Wireless Sensor Networks
Platform-Based Resource Binding Using a Distributed Register-File Microarchitecture
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
RAMP: Architecture, Language and Compiler
Reliable SRAM Design for Ultra-Low Power Standby
Robust Ultra-Low Power Analog/Mixed-Signal Design
Robust Design of DSP Functional Units for Wireless Communication
Runtime Validation for Memory Ordering Models
SatMate: Satisfiability Checking of Non-clausal Formulas using General Matings
SDC-Based Scheduling Algorithm for Behavioral Synthesis
Self-Repairing SRAM for Silicon Nanotechnologies
Shielding Against Design Flaws with Field Repairable Control Logic
Symbolic Reliability Analysis
Synthesis of an Application-Specific Soft Multiprocessor System
Testable Design for Adaptive Equalizer
VCEGAR: Verilog CounterExample Guided Abstraction and Refinement
Verification-Guided Soft Error Resilience
Vertically-Consistent Spatial Embedding
xPilot: Platform-Based Synthesis System
Yield Estimation under Realistic Descriptions of Parameter Uncertainty
"It’s a small world after all": NoC Performance Optimization via Long Link Insertion
A New Architectural Exploration Paradigm in Behavioral Synthesis
Analysis for Parallelization of Media Applications
Architecture and Compilation for Data Bandwidth Improvement in Configurable Processors
BER Testing for High-Speed Serial Links
Communication and Co-Simulation Infrastructure in Heterogeneous System Integration
Home Gateway Demo
IMPACT Vision
Joint Repeater Insertion and Coding
Low-cost System-level Testing of Wireless Transceivers
On-Chip Self-Calibration of RF Circuit Using Specification-Driven Built-In Alternate Test
Parameterized Model Order Reduction for Nonlinear Dynamical Systems
Platform Based Design for Wireless Sensor Networks
Predicting Mixed-Signal Specifications With Improved Accuracy Using Optimized Signatures
Production Testing Techniques for Ultra Wideband Transceivers
Pseudo-Functional Testing
Reliable and Low-Power Motion Estimation
Runtime Leakage Reduction through Probability-Aware Vt , Tox Assignment and Logic Restructuring
Soft Error Tolerant Circuit Design: Dual Port Gate
