Dr. Zhang is a Senior Staff Engineer with Intel Corporation, Santa Clara, CA. His current work focuses on System-on-Chip (SoC) architecture and low-power design methodologies. He has extensive research experiences in the areas of Micro-Electro-Mechanical Systems (MEMS), soft error rate (SER), error-tolerant circuit design, VLSI test, and cache design. He has published more than thirty papers and holds twelve issued or pending U.S. patents in the aforementioned areas. He serves on the program committees of several IEEE conferences and symposia. He has received various research, teaching, and recognition awards from UIUC and Intel.