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Karthik Gururaj
    University of California, Los Angeles

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Bio:Name:Karthik Gururaj Date of Birth:9th May, 1984 Gender:Male E-Mail:karthikg@cs.ucla.edu Currently Pursuing PhD degree in Computer Science under Prof.Jason Cong, University of California Los Angeles B. Tech in Computer Science and Engg.Indian Institute of Technology Madras (GPA 8.79/10) Courses Taken: ¯ Design of circuits and systems in VLSI ¯ Advanced Computer Architecture. ¯ Graph Theory ¯ Fault tolerant computer systems Relevant Courses (B. Tech): ¯ CAD for VLSI ¯ Computer Systems Design ¯ Computer Organization ¯ Digital System Testing and Testable Design ¯ Language Translators ¯ Minor in Operations Research Skills: Computer Languages: C/C++, Java , Perl, x86 assembly (nasm). Familiar with working with: Solaris, Linux, Windows CAD tools :Synopsys PrimeTime, Star-RCXT, Spice, Magic. Other utilities familiar with:YACC, Flex Current Project: ¯ Research assistant under Dr. Jason Cong , Professor Computer Science Dept UCLA ¯ Application specific processor based design methodology for embedded platforms. The goal is to achieve higher level of design abstraction, design reuse, flexibility and automatic synthesis from high level specification. ¯ Currently, working on ¯xpilot¯ a high level synthesis tool being developed at UCLA. Academic Projects: B. Tech Final year project : Worked on generating power virus for a digital circuit under the guidance of Dr. V Kamakoti¯Asst. Professor, Dept. of Computer Science and Engineering, IIT Madras. The work involved developing an ATPG based technique to obtain a pair of input vectors which when applied to a CMOS circuit would lead to high power dissipation. This technique is useful in industry to determine the heat dissipated by a circuit and hence determining the cooling equired. ¯Design of a pipelined superscalar processor as part of CAD for VLSI course : Designed a RTL verilog model of a multiprocessor system sharing common Main Memory module. Each processor in the system implemented Tomasulo technique to achieve the goal of having superscalar processors. Implemented MESI protocol for cache coherency. Used MAGMA flow to get the final placed and routed design.

¯Compiler for subset of Pascal as part of Compilers Design Course : The compiler works for a subset of Pascal and converts source program to x86 assembly code which can be assembled using nasm. The compiler was written in C and used YACC and flex. ¯Implemented a model of simple file system in Java as part of Operating Systems course. The model could read and write blocks of data to main memory module by issuing I/O system calls to an existing model of an operating system written in Java which simulated disk behavior. Also, buffer cache system was implemented. Internship: ¯Worked as summer intern in Open Silicon, Bangalore in the period May-July, 2005 : Was part of the methodology group trying to develop an automatic flow from RTL to GDS-2 using Synopsys tools.Worked on parasitic extraction of clock networks in large designs and doing both static (PrimeTime)and dynamic (Spice simulation) timing analysis on them. Hobbies :Reading science fiction novels and playing cricket and table-tennis.

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