My research interests focus on shared resource management for Chip-Multiprocessor (CMP) systems. In particular, I investigate hardware techniques at various granularity levels to assist in the management of the last-level shared CMP caches, targeting performance throughput and quality of service. I am also interested in techniques that exploit potential parallelism hidden in multi-threaded applications on CMP systems. I have looked into transactional memory as well as data-centric synchronization approaches to explore potential thread-level parallelism in modern workloads.

I led the Computer Architecture Reading Group (CARG) in the Departments of Electrical Engineering and Computer Science at Princeton University from 2007 to 2009.

I graduated from the School of Electrical and Computer Engineering at Cornell University in 2006 where I worked with Professor Jose Martinez. My undergraduate thesis is on the predictability of microprocessor LLC miss values.