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Prateek Bhansali
University of California, Berkeley
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http://laoo.dtc.umn.edu/publicWiki/tiki-index.php?page=bhansaliPublicHomePage
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Prateek Bhansali obtained his B. Tech. degree in electrical engineering from the Indian Institute of Technology, Kanpur, India in 2007. He is currently (2009) a third year graduate student in the Ph.D. program in electrical engineering and computer sciences at University of California at Berkeley under Prof. Jaijeet Roychowdhury. He is interested in the area of RF circuit simulation, circuit macromodeling techniques and biological CAD. He spent his 2008 summer at the Strategic CAD Labs, Intel, Hillsboro working on efficient implementation of MCSM macromodeling technique for I/O buffer circuits. During 2009 summer, he worked on L-1 norm minimization and moment matching based LTI model order reduction at Sandia National Laboratories.
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